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1 From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001
2 From: Sam Edwards <cfsworks@gmail.com>
3 Date: Wed, 11 Sep 2024 19:50:30 -0700
4 Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
5
6 These pinctrls manage the low-speed PCIe signals:
7 - CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
8 request that external clock-generation circuitry provide a clock.
9 - PERST#: An input on the RK3588 in EP mode, used to detect a reset
10 signal from the RC. In RC mode, the hardware does not use this signal:
11 Linux itself generates it by putting the pin in GPIO mode.
12 - WAKE#: In EP mode, this is an output; in RC mode, this is an input.
13
14 Each of these signals serves a distinct purpose, and more importantly,
15 PERST# should not be muxed when the RK3588 is in the RC role. Bundling
16 them together in pinctrl groups prevents proper use: indeed, almost none
17 of the current board-specific .dts files make any use of them.
18 (Exception: Rock 5A recently had a patch land that misuses _pins; this
19 patch corrects that.)
20
21 However, on some RK3588 boards, the PCIe 3 controller will indefinitely
22 stall the boot if CLKREQ# is not muxed (details in the next patch).
23 This patch unbundles the signals to allow them to be used.
24
25 Signed-off-by: Sam Edwards <CFSworks@gmail.com>
26 Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
27 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
28
29 --- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
30 +++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
31 @@ -1612,23 +1612,43 @@
32
33 pcie20x1 {
34 /omit-if-no-ref/
35 - pcie20x1m0_pins: pcie20x1m0-pins {
36 + pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
37 rockchip,pins =
38 /* pcie20x1_2_clkreqn_m0 */
39 - <3 RK_PC7 4 &pcfg_pull_none>,
40 + <3 RK_PC7 4 &pcfg_pull_none>;
41 + };
42 +
43 + /omit-if-no-ref/
44 + pcie20x1m0_perstn: pcie20x1m0-perstn {
45 + rockchip,pins =
46 /* pcie20x1_2_perstn_m0 */
47 - <3 RK_PD1 4 &pcfg_pull_none>,
48 + <3 RK_PD1 4 &pcfg_pull_none>;
49 + };
50 +
51 + /omit-if-no-ref/
52 + pcie20x1m0_waken: pcie20x1m0-waken {
53 + rockchip,pins =
54 /* pcie20x1_2_waken_m0 */
55 <3 RK_PD0 4 &pcfg_pull_none>;
56 };
57
58 /omit-if-no-ref/
59 - pcie20x1m1_pins: pcie20x1m1-pins {
60 + pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
61 rockchip,pins =
62 /* pcie20x1_2_clkreqn_m1 */
63 - <4 RK_PB7 4 &pcfg_pull_none>,
64 + <4 RK_PB7 4 &pcfg_pull_none>;
65 + };
66 +
67 + /omit-if-no-ref/
68 + pcie20x1m1_perstn: pcie20x1m1-perstn {
69 + rockchip,pins =
70 /* pcie20x1_2_perstn_m1 */
71 - <4 RK_PC1 4 &pcfg_pull_none>,
72 + <4 RK_PC1 4 &pcfg_pull_none>;
73 + };
74 +
75 + /omit-if-no-ref/
76 + pcie20x1m1_waken: pcie20x1m1-waken {
77 + rockchip,pins =
78 /* pcie20x1_2_waken_m1 */
79 <4 RK_PC0 4 &pcfg_pull_none>;
80 };
81 @@ -1654,52 +1674,127 @@
82
83 pcie30x1 {
84 /omit-if-no-ref/
85 - pcie30x1m0_pins: pcie30x1m0-pins {
86 + pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
87 rockchip,pins =
88 /* pcie30x1_0_clkreqn_m0 */
89 - <0 RK_PC0 12 &pcfg_pull_none>,
90 + <0 RK_PC0 12 &pcfg_pull_none>;
91 + };
92 +
93 + /omit-if-no-ref/
94 + pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
95 + rockchip,pins =
96 /* pcie30x1_0_perstn_m0 */
97 - <0 RK_PC5 12 &pcfg_pull_none>,
98 + <0 RK_PC5 12 &pcfg_pull_none>;
99 + };
100 +
101 + /omit-if-no-ref/
102 + pcie30x1m0_0_waken: pcie30x1m0-0-waken {
103 + rockchip,pins =
104 /* pcie30x1_0_waken_m0 */
105 - <0 RK_PC4 12 &pcfg_pull_none>,
106 + <0 RK_PC4 12 &pcfg_pull_none>;
107 + };
108 +
109 + /omit-if-no-ref/
110 + pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
111 + rockchip,pins =
112 /* pcie30x1_1_clkreqn_m0 */
113 - <0 RK_PB5 12 &pcfg_pull_none>,
114 + <0 RK_PB5 12 &pcfg_pull_none>;
115 + };
116 +
117 + /omit-if-no-ref/
118 + pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
119 + rockchip,pins =
120 /* pcie30x1_1_perstn_m0 */
121 - <0 RK_PB7 12 &pcfg_pull_none>,
122 + <0 RK_PB7 12 &pcfg_pull_none>;
123 + };
124 +
125 + /omit-if-no-ref/
126 + pcie30x1m0_1_waken: pcie30x1m0-1-waken {
127 + rockchip,pins =
128 /* pcie30x1_1_waken_m0 */
129 <0 RK_PB6 12 &pcfg_pull_none>;
130 };
131
132 /omit-if-no-ref/
133 - pcie30x1m1_pins: pcie30x1m1-pins {
134 + pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
135 rockchip,pins =
136 /* pcie30x1_0_clkreqn_m1 */
137 - <4 RK_PA3 4 &pcfg_pull_none>,
138 + <4 RK_PA3 4 &pcfg_pull_none>;
139 + };
140 +
141 + /omit-if-no-ref/
142 + pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
143 + rockchip,pins =
144 /* pcie30x1_0_perstn_m1 */
145 - <4 RK_PA5 4 &pcfg_pull_none>,
146 + <4 RK_PA5 4 &pcfg_pull_none>;
147 + };
148 +
149 + /omit-if-no-ref/
150 + pcie30x1m1_0_waken: pcie30x1m1-0-waken {
151 + rockchip,pins =
152 /* pcie30x1_0_waken_m1 */
153 - <4 RK_PA4 4 &pcfg_pull_none>,
154 + <4 RK_PA4 4 &pcfg_pull_none>;
155 + };
156 +
157 + /omit-if-no-ref/
158 + pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
159 + rockchip,pins =
160 /* pcie30x1_1_clkreqn_m1 */
161 - <4 RK_PA0 4 &pcfg_pull_none>,
162 + <4 RK_PA0 4 &pcfg_pull_none>;
163 + };
164 +
165 + /omit-if-no-ref/
166 + pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
167 + rockchip,pins =
168 /* pcie30x1_1_perstn_m1 */
169 - <4 RK_PA2 4 &pcfg_pull_none>,
170 + <4 RK_PA2 4 &pcfg_pull_none>;
171 + };
172 +
173 + /omit-if-no-ref/
174 + pcie30x1m1_1_waken: pcie30x1m1-1-waken {
175 + rockchip,pins =
176 /* pcie30x1_1_waken_m1 */
177 <4 RK_PA1 4 &pcfg_pull_none>;
178 };
179
180 /omit-if-no-ref/
181 - pcie30x1m2_pins: pcie30x1m2-pins {
182 + pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
183 rockchip,pins =
184 /* pcie30x1_0_clkreqn_m2 */
185 - <1 RK_PB5 4 &pcfg_pull_none>,
186 + <1 RK_PB5 4 &pcfg_pull_none>;
187 + };
188 +
189 + /omit-if-no-ref/
190 + pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
191 + rockchip,pins =
192 /* pcie30x1_0_perstn_m2 */
193 - <1 RK_PB4 4 &pcfg_pull_none>,
194 + <1 RK_PB4 4 &pcfg_pull_none>;
195 + };
196 +
197 + /omit-if-no-ref/
198 + pcie30x1m2_0_waken: pcie30x1m2-0-waken {
199 + rockchip,pins =
200 /* pcie30x1_0_waken_m2 */
201 - <1 RK_PB3 4 &pcfg_pull_none>,
202 + <1 RK_PB3 4 &pcfg_pull_none>;
203 + };
204 +
205 + /omit-if-no-ref/
206 + pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
207 + rockchip,pins =
208 /* pcie30x1_1_clkreqn_m2 */
209 - <1 RK_PA0 4 &pcfg_pull_none>,
210 + <1 RK_PA0 4 &pcfg_pull_none>;
211 + };
212 +
213 + /omit-if-no-ref/
214 + pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
215 + rockchip,pins =
216 /* pcie30x1_1_perstn_m2 */
217 - <1 RK_PA7 4 &pcfg_pull_none>,
218 + <1 RK_PA7 4 &pcfg_pull_none>;
219 + };
220 +
221 + /omit-if-no-ref/
222 + pcie30x1m2_1_waken: pcie30x1m2-1-waken {
223 + rockchip,pins =
224 /* pcie30x1_1_waken_m2 */
225 <1 RK_PA1 4 &pcfg_pull_none>;
226 };
227 @@ -1721,45 +1816,85 @@
228
229 pcie30x2 {
230 /omit-if-no-ref/
231 - pcie30x2m0_pins: pcie30x2m0-pins {
232 + pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
233 rockchip,pins =
234 /* pcie30x2_clkreqn_m0 */
235 - <0 RK_PD1 12 &pcfg_pull_none>,
236 + <0 RK_PD1 12 &pcfg_pull_none>;
237 + };
238 +
239 + /omit-if-no-ref/
240 + pcie30x2m0_perstn: pcie30x2m0-perstn {
241 + rockchip,pins =
242 /* pcie30x2_perstn_m0 */
243 - <0 RK_PD4 12 &pcfg_pull_none>,
244 + <0 RK_PD4 12 &pcfg_pull_none>;
245 + };
246 +
247 + /omit-if-no-ref/
248 + pcie30x2m0_waken: pcie30x2m0-waken {
249 + rockchip,pins =
250 /* pcie30x2_waken_m0 */
251 <0 RK_PD2 12 &pcfg_pull_none>;
252 };
253
254 /omit-if-no-ref/
255 - pcie30x2m1_pins: pcie30x2m1-pins {
256 + pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
257 rockchip,pins =
258 /* pcie30x2_clkreqn_m1 */
259 - <4 RK_PA6 4 &pcfg_pull_none>,
260 + <4 RK_PA6 4 &pcfg_pull_none>;
261 + };
262 +
263 + /omit-if-no-ref/
264 + pcie30x2m1_perstn: pcie30x2m1-perstn {
265 + rockchip,pins =
266 /* pcie30x2_perstn_m1 */
267 - <4 RK_PB0 4 &pcfg_pull_none>,
268 + <4 RK_PB0 4 &pcfg_pull_none>;
269 + };
270 +
271 + /omit-if-no-ref/
272 + pcie30x2m1_waken: pcie30x2m1-waken {
273 + rockchip,pins =
274 /* pcie30x2_waken_m1 */
275 <4 RK_PA7 4 &pcfg_pull_none>;
276 };
277
278 /omit-if-no-ref/
279 - pcie30x2m2_pins: pcie30x2m2-pins {
280 + pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
281 rockchip,pins =
282 /* pcie30x2_clkreqn_m2 */
283 - <3 RK_PD2 4 &pcfg_pull_none>,
284 + <3 RK_PD2 4 &pcfg_pull_none>;
285 + };
286 +
287 + /omit-if-no-ref/
288 + pcie30x2m2_perstn: pcie30x2m2-perstn {
289 + rockchip,pins =
290 /* pcie30x2_perstn_m2 */
291 - <3 RK_PD4 4 &pcfg_pull_none>,
292 + <3 RK_PD4 4 &pcfg_pull_none>;
293 + };
294 +
295 + /omit-if-no-ref/
296 + pcie30x2m2_waken: pcie30x2m2-waken {
297 + rockchip,pins =
298 /* pcie30x2_waken_m2 */
299 <3 RK_PD3 4 &pcfg_pull_none>;
300 };
301
302 /omit-if-no-ref/
303 - pcie30x2m3_pins: pcie30x2m3-pins {
304 + pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
305 rockchip,pins =
306 /* pcie30x2_clkreqn_m3 */
307 - <1 RK_PD7 4 &pcfg_pull_none>,
308 + <1 RK_PD7 4 &pcfg_pull_none>;
309 + };
310 +
311 + /omit-if-no-ref/
312 + pcie30x2m3_perstn: pcie30x2m3-perstn {
313 + rockchip,pins =
314 /* pcie30x2_perstn_m3 */
315 - <1 RK_PB7 4 &pcfg_pull_none>,
316 + <1 RK_PB7 4 &pcfg_pull_none>;
317 + };
318 +
319 + /omit-if-no-ref/
320 + pcie30x2m3_waken: pcie30x2m3-waken {
321 + rockchip,pins =
322 /* pcie30x2_waken_m3 */
323 <1 RK_PB6 4 &pcfg_pull_none>;
324 };
325 @@ -1774,45 +1909,85 @@
326
327 pcie30x4 {
328 /omit-if-no-ref/
329 - pcie30x4m0_pins: pcie30x4m0-pins {
330 + pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
331 rockchip,pins =
332 /* pcie30x4_clkreqn_m0 */
333 - <0 RK_PC6 12 &pcfg_pull_none>,
334 + <0 RK_PC6 12 &pcfg_pull_none>;
335 + };
336 +
337 + /omit-if-no-ref/
338 + pcie30x4m0_perstn: pcie30x4m0-perstn {
339 + rockchip,pins =
340 /* pcie30x4_perstn_m0 */
341 - <0 RK_PD0 12 &pcfg_pull_none>,
342 + <0 RK_PD0 12 &pcfg_pull_none>;
343 + };
344 +
345 + /omit-if-no-ref/
346 + pcie30x4m0_waken: pcie30x4m0-waken {
347 + rockchip,pins =
348 /* pcie30x4_waken_m0 */
349 <0 RK_PC7 12 &pcfg_pull_none>;
350 };
351
352 /omit-if-no-ref/
353 - pcie30x4m1_pins: pcie30x4m1-pins {
354 + pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
355 rockchip,pins =
356 /* pcie30x4_clkreqn_m1 */
357 - <4 RK_PB4 4 &pcfg_pull_none>,
358 + <4 RK_PB4 4 &pcfg_pull_none>;
359 + };
360 +
361 + /omit-if-no-ref/
362 + pcie30x4m1_perstn: pcie30x4m1-perstn {
363 + rockchip,pins =
364 /* pcie30x4_perstn_m1 */
365 - <4 RK_PB6 4 &pcfg_pull_none>,
366 + <4 RK_PB6 4 &pcfg_pull_none>;
367 + };
368 +
369 + /omit-if-no-ref/
370 + pcie30x4m1_waken: pcie30x4m1-waken {
371 + rockchip,pins =
372 /* pcie30x4_waken_m1 */
373 <4 RK_PB5 4 &pcfg_pull_none>;
374 };
375
376 /omit-if-no-ref/
377 - pcie30x4m2_pins: pcie30x4m2-pins {
378 + pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
379 rockchip,pins =
380 /* pcie30x4_clkreqn_m2 */
381 - <3 RK_PC4 4 &pcfg_pull_none>,
382 + <3 RK_PC4 4 &pcfg_pull_none>;
383 + };
384 +
385 + /omit-if-no-ref/
386 + pcie30x4m2_perstn: pcie30x4m2-perstn {
387 + rockchip,pins =
388 /* pcie30x4_perstn_m2 */
389 - <3 RK_PC6 4 &pcfg_pull_none>,
390 + <3 RK_PC6 4 &pcfg_pull_none>;
391 + };
392 +
393 + /omit-if-no-ref/
394 + pcie30x4m2_waken: pcie30x4m2-waken {
395 + rockchip,pins =
396 /* pcie30x4_waken_m2 */
397 <3 RK_PC5 4 &pcfg_pull_none>;
398 };
399
400 /omit-if-no-ref/
401 - pcie30x4m3_pins: pcie30x4m3-pins {
402 + pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
403 rockchip,pins =
404 /* pcie30x4_clkreqn_m3 */
405 - <1 RK_PB0 4 &pcfg_pull_none>,
406 + <1 RK_PB0 4 &pcfg_pull_none>;
407 + };
408 +
409 + /omit-if-no-ref/
410 + pcie30x4m3_perstn: pcie30x4m3-perstn {
411 + rockchip,pins =
412 /* pcie30x4_perstn_m3 */
413 - <1 RK_PB2 4 &pcfg_pull_none>,
414 + <1 RK_PB2 4 &pcfg_pull_none>;
415 + };
416 +
417 + /omit-if-no-ref/
418 + pcie30x4m3_waken: pcie30x4m3-waken {
419 + rockchip,pins =
420 /* pcie30x4_waken_m3 */
421 <1 RK_PB1 4 &pcfg_pull_none>;
422 };
423 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
424 +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
425 @@ -310,7 +310,7 @@
426 };
427
428 &pcie2x1l2 {
429 - pinctrl-0 = <&pcie20x1m0_pins>;
430 + pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
431 pinctrl-names = "default";
432 reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
433 vpcie3v3-supply = <&vcc3v3_wf>;
434 @@ -328,6 +328,10 @@
435 pow_en: pow-en {
436 rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
437 };
438 +
439 + pcie2_reset: pcie2-reset {
440 + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
441 + };
442 };
443
444 power {
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