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1 From 8d43287120ce6437e7a77e735d99137f3fdb3ae9 Mon Sep 17 00:00:00 2001
2 From: Jonas Jelonek <jelonek.jonas@gmail.com>
3 Date: Sat, 27 Sep 2025 10:19:31 +0000
4 Subject: [PATCH] i2c: rtl9300: add support for RTL9310 I2C controller
5
6 Add support for the internal I2C controllers of RTL9310 series based
7 SoCs to the driver for RTL9300. Add register definitions, chip-specific
8 functions and compatible strings for known RTL9310-based SoCs RTL9311,
9 RTL9312 and RTL9313.
10
11 Make use of a new device tree property 'realtek,scl' which needs to be
12 specified in case both or only the second master is used. This is
13 required due how the register layout changed in contrast to RTL9300,
14 which has SCL selection in a global register instead of a
15 master-specific one.
16
17 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
18 Tested-by: Sven Eckelmann <sven@narfation.org>
19 Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
20 Tested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
21 Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
22 Link: https://lore.kernel.org/r/20250927101931.71575-10-jelonek.jonas@gmail.com
23
24 diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9300.c
25 index c67463228604..4723e48cfe18 100644
26 --- a/drivers/i2c/busses/i2c-rtl9300.c
27 +++ b/drivers/i2c/busses/i2c-rtl9300.c
28 @@ -60,14 +60,16 @@ struct rtl9300_i2c_drv_data {
29 };
30
31 #define RTL9300_I2C_MUX_NCHAN 8
32 +#define RTL9310_I2C_MUX_NCHAN 12
33
34 struct rtl9300_i2c {
35 struct regmap *regmap;
36 struct device *dev;
37 - struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN];
38 + struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN];
39 struct regmap_field *fields[F_NUM_FIELDS];
40 u32 reg_base;
41 u32 data_reg;
42 + u8 scl_num;
43 u8 sda_num;
44 struct mutex lock;
45 };
46 @@ -98,6 +100,12 @@ struct rtl9300_i2c_xfer {
47 #define RTL9300_I2C_MST_DATA_WORD3 0x14
48 #define RTL9300_I2C_MST_GLB_CTRL 0x384
49
50 +#define RTL9310_I2C_MST_IF_CTRL 0x1004
51 +#define RTL9310_I2C_MST_IF_SEL 0x1008
52 +#define RTL9310_I2C_MST_CTRL 0x0
53 +#define RTL9310_I2C_MST_MEMADDR_CTRL 0x4
54 +#define RTL9310_I2C_MST_DATA_CTRL 0x8
55 +
56 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
57 {
58 int ret;
59 @@ -114,6 +122,11 @@ static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
60 return regmap_field_write(i2c->fields[F_SCL_SEL], 1);
61 }
62
63 +static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
64 +{
65 + return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl));
66 +}
67 +
68 static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)
69 {
70 struct rtl9300_i2c_drv_data *drv_data;
71 @@ -127,7 +140,7 @@ static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_c
72 return ret;
73
74 drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
75 - ret = drv_data->select_scl(i2c, 0);
76 + ret = drv_data->select_scl(i2c, i2c->scl_num);
77 if (ret)
78 return ret;
79
80 @@ -361,7 +374,7 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
81 struct fwnode_handle *child;
82 struct rtl9300_i2c_drv_data *drv_data;
83 struct reg_field fields[F_NUM_FIELDS];
84 - u32 clock_freq, sda_num;
85 + u32 clock_freq, scl_num, sda_num;
86 int ret, i = 0;
87
88 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
89 @@ -379,6 +392,11 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
90 if (ret)
91 return ret;
92
93 + ret = device_property_read_u32(dev, "realtek,scl", &scl_num);
94 + if (ret || scl_num != 1)
95 + scl_num = 0;
96 + i2c->scl_num = (u8)scl_num;
97 +
98 platform_set_drvdata(pdev, i2c);
99
100 drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
101 @@ -474,12 +492,35 @@ static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = {
102 .max_nchan = RTL9300_I2C_MUX_NCHAN,
103 };
104
105 +static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = {
106 + .field_desc = {
107 + [F_SCL_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13),
108 + [F_SDA_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11),
109 + [F_SCL_FREQ] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31),
110 + [F_DEV_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17),
111 + [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21),
112 + [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10),
113 + [F_DATA_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8),
114 + [F_RD_MODE] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4),
115 + [F_RWOP] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2),
116 + [F_I2C_FAIL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1),
117 + [F_I2C_TRIG] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0),
118 + [F_MEM_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23),
119 + },
120 + .select_scl = rtl9310_i2c_select_scl,
121 + .data_reg = RTL9310_I2C_MST_DATA_CTRL,
122 + .max_nchan = RTL9310_I2C_MUX_NCHAN,
123 +};
124
125 static const struct of_device_id i2c_rtl9300_dt_ids[] = {
126 { .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data },
127 { .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data },
128 { .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data },
129 { .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data },
130 + { .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data },
131 + { .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data },
132 + { .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data },
133 + { .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data },
134 {}
135 };
136 MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);
137 --
138 2.48.1
139
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