git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 1b733e878ac1292c6e0f2e9a49685b80c35619b0 Mon Sep 17 00:00:00 2001
   2 From: George Moussalem <george.moussalem@outlook.com>
   3 Date: Mon, 02 Jun 2025 12:50:41 +0400
   4 Subject: [PATCH v3 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset="utf-8"
   7 Content-Transfer-Encoding: 7bit
   8 Message-Id: <20250602-ipq5018-ge-phy-v3-5-0d8f39f402a6@outlook.com>
   9
  10 The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
  11 As such, let's add the GE PHY node to the SoC dtsi.
  12
  13 The LDO controller found in the SoC must be enabled to provide constant
  14 low voltages to the PHY. The mdio-ipq4019 driver already has support
  15 for this, so adding the appropriate TCSR register offset.
  16
  17 In addition, the GE PHY outputs both the RX and TX clocks to the GCC
  18 which gate controls them and routes them back to the PHY itself.
  19 So let's create two DT fixed clocks and register them in the GCC node.
  20
  21 Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
  22 Signed-off-by: George Moussalem <george.moussalem@outlook.com>
  23 ---
  24  arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++---
  25  1 file changed, 23 insertions(+), 3 deletions(-)
  26
  27 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
  28 +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
  29 @@ -23,6 +23,18 @@
  30                         #clock-cells = <0>;
  31                 };
  32
  33 +               gephy_rx_clk: gephy-rx-clk {
  34 +                       compatible = "fixed-clock";
  35 +                       clock-frequency = <125000000>;
  36 +                       #clock-cells = <0>;
  37 +               };
  38 +
  39 +               gephy_tx_clk: gephy-tx-clk {
  40 +                       compatible = "fixed-clock";
  41 +                       clock-frequency = <125000000>;
  42 +                       #clock-cells = <0>;
  43 +               };
  44 +
  45                 sleep_clk: sleep-clk {
  46                         compatible = "fixed-clock";
  47                         #clock-cells = <0>;
  48 @@ -193,7 +205,8 @@
  49
  50                 mdio0: mdio@88000 {
  51                         compatible = "qcom,ipq5018-mdio";
  52 -                       reg = <0x00088000 0x64>;
  53 +                       reg = <0x00088000 0x64>,
  54 +                             <0x019475c4 0x4>;
  55                         #address-cells = <1>;
  56                         #size-cells = <0>;
  57
  58 @@ -201,6 +214,13 @@
  59                         clock-names = "gcc_mdio_ahb_clk";
  60
  61                         status = "disabled";
  62 +
  63 +                       ge_phy: ethernet-phy@7 {
  64 +                               compatible = "ethernet-phy-id004d.d0c0";
  65 +                               reg = <7>;
  66 +
  67 +                               resets = <&gcc GCC_GEPHY_MISC_ARES>;
  68 +                       };
  69                 };
  70
  71                 mdio1: mdio@90000 {
  72 @@ -395,8 +415,8 @@
  73                                  <&pcie0_phy>,
  74                                  <&pcie1_phy>,
  75                                  <0>,
  76 -                                <0>,
  77 -                                <0>,
  78 +                                <&gephy_rx_clk>,
  79 +                                <&gephy_tx_clk>,
  80                                  <0>,
  81                                  <0>;
  82                         #clock-cells = <1>;