git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From e4a9748e7103c47e575459db2b6a77d14f34da2b Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Tue, 14 Jan 2025 00:10:02 +0100
   4 Subject: [PATCH 1/4] clk: en7523: Rework clock handling for different clock
   5  numbers
   6
   7 Airoha EN7581 SoC have additional clock compared to EN7523 but current
   8 driver permits to only support up to EN7523 clock numbers.
   9
  10 To handle this, rework the clock handling and permit to declare the
  11 clocks number in match_data and alloca clk_data based on the compatible
  12 match_data.
  13
  14 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  15 Link: https://lore.kernel.org/r/20250113231030.6735-2-ansuelsmth@gmail.com
  16 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  17 ---
  18  drivers/clk/clk-en7523.c | 14 ++++++++------
  19  1 file changed, 8 insertions(+), 6 deletions(-)
  20
  21 --- a/drivers/clk/clk-en7523.c
  22 +++ b/drivers/clk/clk-en7523.c
  23 @@ -75,6 +75,7 @@ struct en_rst_data {
  24  };
  25
  26  struct en_clk_soc_data {
  27 +       u32 num_clocks;
  28         const struct clk_ops pcie_ops;
  29         int (*hw_init)(struct platform_device *pdev,
  30                        struct clk_hw_onecell_data *clk_data);
  31 @@ -504,8 +505,6 @@ static void en7523_register_clocks(struc
  32         u32 rate;
  33         int i;
  34
  35 -       clk_data->num = EN7523_NUM_CLOCKS;
  36 -
  37         for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
  38                 const struct en_clk_desc *desc = &en7523_base_clks[i];
  39                 u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
  40 @@ -587,8 +586,6 @@ static void en7581_register_clocks(struc
  41
  42         hw = en7523_register_pcie_clk(dev, base);
  43         clk_data->hws[EN7523_CLK_PCIE] = hw;
  44 -
  45 -       clk_data->num = EN7523_NUM_CLOCKS;
  46  }
  47
  48  static int en7523_reset_update(struct reset_controller_dev *rcdev,
  49 @@ -702,13 +699,15 @@ static int en7523_clk_probe(struct platf
  50         struct clk_hw_onecell_data *clk_data;
  51         int r;
  52
  53 +       soc_data = device_get_match_data(&pdev->dev);
  54 +
  55         clk_data = devm_kzalloc(&pdev->dev,
  56 -                               struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
  57 +                               struct_size(clk_data, hws, soc_data->num_clocks),
  58                                 GFP_KERNEL);
  59         if (!clk_data)
  60                 return -ENOMEM;
  61
  62 -       soc_data = device_get_match_data(&pdev->dev);
  63 +       clk_data->num = soc_data->num_clocks;
  64         r = soc_data->hw_init(pdev, clk_data);
  65         if (r)
  66                 return r;
  67 @@ -717,6 +716,7 @@ static int en7523_clk_probe(struct platf
  68  }
  69
  70  static const struct en_clk_soc_data en7523_data = {
  71 +       .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1,
  72         .pcie_ops = {
  73                 .is_enabled = en7523_pci_is_enabled,
  74                 .prepare = en7523_pci_prepare,
  75 @@ -726,6 +726,8 @@ static const struct en_clk_soc_data en75
  76  };
  77
  78  static const struct en_clk_soc_data en7581_data = {
  79 +       /* We increment num_clocks by 1 to account for additional PCIe clock */
  80 +       .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
  81         .pcie_ops = {
  82                 .is_enabled = en7581_pci_is_enabled,
  83                 .enable = en7581_pci_enable,