projects / openwrt / openwrt.git / blob
? search:


92292d7d63f0f530aeca53625ea7f83be002ded8
[openwrt/openwrt.git] /
1 From 5a6ecb27435ef7a67d7bec4543f0c6303f34e8a6 Mon Sep 17 00:00:00 2001
2 From: Jonas Jelonek <jelonek.jonas@gmail.com>
3 Date: Sat, 27 Sep 2025 10:19:23 +0000
4 Subject: [PATCH] i2c: rtl9300: use regmap fields and API for registers
5
6 Adapt the RTL9300 I2C controller driver to use more of the regmap
7 API, especially make use of reg_field and regmap_field instead of macros
8 to represent registers. Most register operations are performed through
9 regmap_field_* API then.
10
11 Handle SCL selection using separate chip-specific functions since this
12 is already known to differ between the Realtek SoC families in such a
13 way that this cannot be properly handled using just a different
14 reg_field.
15
16 This makes it easier to add support for newer generations or to handle
17 differences between specific revisions within a series. Just by
18 defining a separate driver data structure with the corresponding
19 register field definitions and linking it to a new compatible.
20
21 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
22 Tested-by: Sven Eckelmann <sven@narfation.org>
23 Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
24 Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> # On RTL9302C based board
25 Tested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
26 Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
27 Link: https://lore.kernel.org/r/20250927101931.71575-2-jelonek.jonas@gmail.com
28
29 diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9300.c
30 index 9e6232075137..8483bab72146 100644
31 --- a/drivers/i2c/busses/i2c-rtl9300.c
32 +++ b/drivers/i2c/busses/i2c-rtl9300.c
33 @@ -23,97 +23,117 @@ struct rtl9300_i2c_chan {
34 u8 sda_pin;
35 };
36
37 +enum rtl9300_i2c_reg_scope {
38 + REG_SCOPE_GLOBAL,
39 + REG_SCOPE_MASTER,
40 +};
41 +
42 +struct rtl9300_i2c_reg_field {
43 + struct reg_field field;
44 + enum rtl9300_i2c_reg_scope scope;
45 +};
46 +
47 +enum rtl9300_i2c_reg_fields {
48 + F_DATA_WIDTH = 0,
49 + F_DEV_ADDR,
50 + F_I2C_FAIL,
51 + F_I2C_TRIG,
52 + F_MEM_ADDR,
53 + F_MEM_ADDR_WIDTH,
54 + F_RD_MODE,
55 + F_RWOP,
56 + F_SCL_FREQ,
57 + F_SCL_SEL,
58 + F_SDA_OUT_SEL,
59 + F_SDA_SEL,
60 +
61 + /* keep last */
62 + F_NUM_FIELDS
63 +};
64 +
65 +struct rtl9300_i2c_drv_data {
66 + struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS];
67 + int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl);
68 + u32 data_reg;
69 + u8 max_nchan;
70 +};
71 +
72 #define RTL9300_I2C_MUX_NCHAN 8
73
74 struct rtl9300_i2c {
75 struct regmap *regmap;
76 struct device *dev;
77 struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN];
78 + struct regmap_field *fields[F_NUM_FIELDS];
79 u32 reg_base;
80 + u32 data_reg;
81 u8 sda_pin;
82 struct mutex lock;
83 };
84
85 #define RTL9300_I2C_MST_CTRL1 0x0
86 -#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8
87 -#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8)
88 -#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4
89 -#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4)
90 -#define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3)
91 -#define RTL9300_I2C_MST_CTRL1_RWOP BIT(2)
92 -#define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1)
93 -#define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0)
94 #define RTL9300_I2C_MST_CTRL2 0x4
95 -#define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15)
96 -#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8
97 -#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8)
98 -#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4
99 -#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4)
100 -#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2
101 -#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2)
102 -#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0
103 -#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0)
104 #define RTL9300_I2C_MST_DATA_WORD0 0x8
105 #define RTL9300_I2C_MST_DATA_WORD1 0xc
106 #define RTL9300_I2C_MST_DATA_WORD2 0x10
107 #define RTL9300_I2C_MST_DATA_WORD3 0x14
108 -
109 #define RTL9300_I2C_MST_GLB_CTRL 0x384
110
111 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
112 {
113 - u32 val, mask;
114 int ret;
115
116 - val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS;
117 - mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK;
118 -
119 - ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
120 + ret = regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len);
121 if (ret)
122 return ret;
123
124 - val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS;
125 - mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK;
126 + return regmap_field_write(i2c->fields[F_MEM_ADDR], reg);
127 +}
128
129 - return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
130 +static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
131 +{
132 + return regmap_field_write(i2c->fields[F_SCL_SEL], 1);
133 }
134
135 static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin)
136 {
137 + struct rtl9300_i2c_drv_data *drv_data;
138 int ret;
139 - u32 val, mask;
140
141 - ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin));
142 + drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
143 +
144 + ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(sda_pin), BIT(sda_pin));
145 if (ret)
146 return ret;
147
148 - val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) |
149 - RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
150 - mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
151 + ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], sda_pin);
152 + if (ret)
153 + return ret;
154
155 - return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
156 + return drv_data->select_scl(i2c, 0);
157 }
158
159 static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan,
160 u16 addr, u16 len)
161 {
162 - u32 val, mask;
163 + int ret;
164
165 if (len < 1 || len > 16)
166 return -EINVAL;
167
168 - val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS;
169 - mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK;
170 -
171 - val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS;
172 - mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK;
173 + ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq);
174 + if (ret)
175 + return ret;
176
177 - val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS;
178 - mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK;
179 + ret = regmap_field_write(i2c->fields[F_DEV_ADDR], addr);
180 + if (ret)
181 + return ret;
182
183 - mask |= RTL9300_I2C_MST_CTRL2_RD_MODE;
184 + ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (len - 1) & 0xf);
185 + if (ret)
186 + return ret;
187
188 - return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
189 + return regmap_field_write(i2c->fields[F_RD_MODE], 0);
190 }
191
192 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
193 @@ -124,8 +144,7 @@ static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
194 if (len > 16)
195 return -EIO;
196
197 - ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
198 - vals, ARRAY_SIZE(vals));
199 + ret = regmap_bulk_read(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));
200 if (ret)
201 return ret;
202
203 @@ -152,52 +171,49 @@ static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)
204 vals[reg] |= buf[i] << shift;
205 }
206
207 - return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
208 - vals, ARRAY_SIZE(vals));
209 + return regmap_bulk_write(i2c->regmap, i2c->data_reg, vals, ARRAY_SIZE(vals));
210 }
211
212 static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)
213 {
214 - return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data);
215 + return regmap_write(i2c->regmap, i2c->data_reg, data);
216 }
217
218 static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write,
219 int size, union i2c_smbus_data *data, int len)
220 {
221 - u32 val, mask;
222 + u32 val;
223 int ret;
224
225 - val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0;
226 - mask = RTL9300_I2C_MST_CTRL1_RWOP;
227 -
228 - val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
229 - mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
230 + ret = regmap_field_write(i2c->fields[F_RWOP], read_write == I2C_SMBUS_WRITE);
231 + if (ret)
232 + return ret;
233
234 - ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
235 + ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1);
236 if (ret)
237 return ret;
238
239 - ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1,
240 - val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 100000);
241 + ret = regmap_field_read_poll_timeout(i2c->fields[F_I2C_TRIG], val, !val, 100, 100000);
242 if (ret)
243 return ret;
244
245 - if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL)
246 + ret = regmap_field_read(i2c->fields[F_I2C_FAIL], &val);
247 + if (ret)
248 + return ret;
249 + if (val)
250 return -EIO;
251
252 if (read_write == I2C_SMBUS_READ) {
253 switch (size) {
254 case I2C_SMBUS_BYTE:
255 case I2C_SMBUS_BYTE_DATA:
256 - ret = regmap_read(i2c->regmap,
257 - i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
258 + ret = regmap_read(i2c->regmap, i2c->data_reg, &val);
259 if (ret)
260 return ret;
261 data->byte = val & 0xff;
262 break;
263 case I2C_SMBUS_WORD_DATA:
264 - ret = regmap_read(i2c->regmap,
265 - i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
266 + ret = regmap_read(i2c->regmap, i2c->data_reg, &val);
267 if (ret)
268 return ret;
269 data->word = val & 0xffff;
270 @@ -355,9 +371,11 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
271 {
272 struct device *dev = &pdev->dev;
273 struct rtl9300_i2c *i2c;
274 + struct fwnode_handle *child;
275 + struct rtl9300_i2c_drv_data *drv_data;
276 + struct reg_field fields[F_NUM_FIELDS];
277 u32 clock_freq, sda_pin;
278 int ret, i = 0;
279 - struct fwnode_handle *child;
280
281 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
282 if (!i2c)
283 @@ -376,9 +394,22 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
284
285 platform_set_drvdata(pdev, i2c);
286
287 - if (device_get_child_node_count(dev) > RTL9300_I2C_MUX_NCHAN)
288 + drv_data = (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->dev);
289 + if (device_get_child_node_count(dev) > drv_data->max_nchan)
290 return dev_err_probe(dev, -EINVAL, "Too many channels\n");
291
292 + i2c->data_reg = i2c->reg_base + drv_data->data_reg;
293 + for (i = 0; i < F_NUM_FIELDS; i++) {
294 + fields[i] = drv_data->field_desc[i].field;
295 + if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER)
296 + fields[i].reg += i2c->reg_base;
297 + }
298 + ret = devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields,
299 + fields, F_NUM_FIELDS);
300 + if (ret)
301 + return ret;
302 +
303 + i = 0;
304 device_for_each_child_node(dev, child) {
305 struct rtl9300_i2c_chan *chan = &i2c->chans[i];
306 struct i2c_adapter *adap = &chan->adap;
307 @@ -395,7 +426,6 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
308 case I2C_MAX_STANDARD_MODE_FREQ:
309 chan->bus_freq = RTL9300_I2C_STD_FREQ;
310 break;
311 -
312 case I2C_MAX_FAST_MODE_FREQ:
313 chan->bus_freq = RTL9300_I2C_FAST_FREQ;
314 break;
315 @@ -427,11 +457,37 @@ static int rtl9300_i2c_probe(struct platform_device *pdev)
316 return 0;
317 }
318
319 +#define GLB_REG_FIELD(reg, msb, lsb) \
320 + { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL }
321 +#define MST_REG_FIELD(reg, msb, lsb) \
322 + { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER }
323 +
324 +static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = {
325 + .field_desc = {
326 + [F_MEM_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31),
327 + [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6),
328 + [F_SCL_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3),
329 + [F_RWOP] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2),
330 + [F_I2C_FAIL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1),
331 + [F_I2C_TRIG] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0),
332 + [F_RD_MODE] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15),
333 + [F_DEV_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14),
334 + [F_DATA_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7),
335 + [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3),
336 + [F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1),
337 + [F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7),
338 + },
339 + .select_scl = rtl9300_i2c_select_scl,
340 + .data_reg = RTL9300_I2C_MST_DATA_WORD0,
341 + .max_nchan = RTL9300_I2C_MUX_NCHAN,
342 +};
343 +
344 +
345 static const struct of_device_id i2c_rtl9300_dt_ids[] = {
346 - { .compatible = "realtek,rtl9301-i2c" },
347 - { .compatible = "realtek,rtl9302b-i2c" },
348 - { .compatible = "realtek,rtl9302c-i2c" },
349 - { .compatible = "realtek,rtl9303-i2c" },
350 + { .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data },
351 + { .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data },
352 + { .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data },
353 + { .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data },
354 {}
355 };
356 MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);
357 --
358 2.48.1
359
OpenWrt Source Repository