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1 From 2f435137a0484f11b47554281091ef4908f8cb31 Mon Sep 17 00:00:00 2001
2 From: Sky Huang <skylake.huang@mediatek.com>
3 Date: Thu, 13 Feb 2025 16:05:49 +0800
4 Subject: [PATCH 1/5] net: phy: mediatek: Change to more meaningful macros
5
6 Replace magic number with more meaningful macros in mtk-ge.c.
7 Also, move some common macros into mtk-phy-lib.c.
8
9 Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
10 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
11 Link: https://patch.msgid.link/20250213080553.921434-2-SkyLake.Huang@mediatek.com
12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
13 ---
14 drivers/net/phy/mediatek/mtk-ge-soc.c | 1 -
15 drivers/net/phy/mediatek/mtk-ge.c | 71 +++++++++++++++++++++------
16 drivers/net/phy/mediatek/mtk.h | 2 +
17 3 files changed, 57 insertions(+), 17 deletions(-)
18
19 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
20 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
21 @@ -24,7 +24,6 @@
22 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
23
24 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
25 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
26
27 #define ANALOG_INTERNAL_OPERATION_MAX_US 20
28 #define TXRESERVE_MIN 0
29 --- a/drivers/net/phy/mediatek/mtk-ge.c
30 +++ b/drivers/net/phy/mediatek/mtk-ge.c
31 @@ -8,13 +8,31 @@
32 #define MTK_GPHY_ID_MT7530 0x03a29412
33 #define MTK_GPHY_ID_MT7531 0x03a29441
34
35 -#define MTK_EXT_PAGE_ACCESS 0x1f
36 -#define MTK_PHY_PAGE_STANDARD 0x0000
37 -#define MTK_PHY_PAGE_EXTENDED 0x0001
38 -#define MTK_PHY_PAGE_EXTENDED_2 0x0002
39 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003
40 -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
41 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
42 +#define MTK_PHY_PAGE_EXTENDED_1 0x0001
43 +#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
44 +#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
45 +
46 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002
47 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
48 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
49 +
50 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
51 +
52 +/* Registers on MDIO_MMD_VEND1 */
53 +#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
54 +#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
55 +#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
56 +#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
57 +
58 +#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
59 +#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
60 +
61 +#define MTK_PHY_RXADC_CTRL_RG7 0xc6
62 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
63 +
64 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
65 +#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
66 +#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
67
68 static void mtk_gephy_config_init(struct phy_device *phydev)
69 {
70 @@ -22,7 +40,9 @@ static void mtk_gephy_config_init(struct
71 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
72
73 /* Enable HW auto downshift */
74 - phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
75 + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
76 + MTK_PHY_AUX_CTRL_AND_STATUS,
77 + 0, MTK_PHY_ENABLE_DOWNSHIFT);
78
79 /* Increase SlvDPSready time */
80 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
81 @@ -32,10 +52,20 @@ static void mtk_gephy_config_init(struct
82 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
83
84 /* Adjust 100_mse_threshold */
85 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
86 -
87 - /* Disable mcc */
88 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
89 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
90 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
91 + MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
92 + MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
93 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
94 + 0xff) |
95 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
96 + 0xff));
97 +
98 + /* If echo time is narrower than 0x3, it will be regarded as noise */
99 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
100 + MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
101 + MTK_MCC_NEARECHO_OFFSET_MASK,
102 + FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
103 }
104
105 static int mt7530_phy_config_init(struct phy_device *phydev)
106 @@ -43,7 +73,8 @@ static int mt7530_phy_config_init(struct
107 mtk_gephy_config_init(phydev);
108
109 /* Increase post_update_timer */
110 - phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
111 + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
112 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
113
114 return 0;
115 }
116 @@ -54,11 +85,19 @@ static int mt7531_phy_config_init(struct
117
118 /* PHY link down power saving enable */
119 phy_set_bits(phydev, 0x17, BIT(4));
120 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
121 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
122 + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
123 + FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
124
125 /* Set TX Pair delay selection */
126 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
127 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
128 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
129 + MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
130 + FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
131 + FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
132 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
133 + MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
134 + FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
135 + FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
136
137 return 0;
138 }
139 --- a/drivers/net/phy/mediatek/mtk.h
140 +++ b/drivers/net/phy/mediatek/mtk.h
141 @@ -9,6 +9,8 @@
142 #define _MTK_EPHY_H_
143
144 #define MTK_EXT_PAGE_ACCESS 0x1f
145 +#define MTK_PHY_PAGE_STANDARD 0x0000
146 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
147
148 /* Registers on MDIO_MMD_VEND2 */
149 #define MTK_PHY_LED0_ON_CTRL 0x24
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