git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 849d9db170fc8a03ce9f64133a1d0cd46c135105 Mon Sep 17 00:00:00 2001
   2 From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
   3 Date: Tue, 4 Feb 2025 16:35:46 +0100
   4 Subject: [PATCH] dt-bindings: reset: Add SCMI reset IDs for RK3588
   5
   6 When TF-A is used to assert/deassert the resets through SCMI, the
   7 IDs communicated to it are different than the ones mainline Linux uses.
   8
   9 Import the list of SCMI reset IDs from mainline TF-A so that devicetrees
  10 can use these IDs more easily.
  11
  12 Co-developed-by: XiaoDong Huang <derrick.huang@rock-chips.com>
  13 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
  14 Acked-by: Conor Dooley <conor.dooley@microchip.com>
  15 Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
  16 Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
  17 ---
  18  .../dt-bindings/reset/rockchip,rk3588-cru.h   | 41 ++++++++++++++++++-
  19  1 file changed, 40 insertions(+), 1 deletion(-)
  20
  21 --- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
  22 +++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
  23 @@ -1,6 +1,6 @@
  24  /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
  25  /*
  26 - * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
  27 + * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd.
  28   * Copyright (c) 2022 Collabora Ltd.
  29   *
  30   * Author: Elaine Zhang <zhangqing@rock-chips.com>
  31 @@ -753,4 +753,43 @@
  32
  33  #define SRST_A_HDMIRX_BIU              660
  34
  35 +/* SCMI Secure Resets */
  36 +
  37 +/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */
  38 +#define SCMI_SRST_A_SECURE_NS_BIU      10
  39 +#define SCMI_SRST_H_SECURE_NS_BIU      11
  40 +#define SCMI_SRST_A_SECURE_S_BIU       12
  41 +#define SCMI_SRST_H_SECURE_S_BIU       13
  42 +#define SCMI_SRST_P_SECURE_S_BIU       14
  43 +#define SCMI_SRST_CRYPTO_CORE          15
  44 +/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */
  45 +#define SCMI_SRST_CRYPTO_PKA           16
  46 +#define SCMI_SRST_CRYPTO_RNG           17
  47 +#define SCMI_SRST_A_CRYPTO             18
  48 +#define SCMI_SRST_H_CRYPTO             19
  49 +#define SCMI_SRST_KEYLADDER_CORE       25
  50 +#define SCMI_SRST_KEYLADDER_RNG                26
  51 +#define SCMI_SRST_A_KEYLADDER          27
  52 +#define SCMI_SRST_H_KEYLADDER          28
  53 +#define SCMI_SRST_P_OTPC_S             29
  54 +#define SCMI_SRST_OTPC_S               30
  55 +#define SCMI_SRST_WDT_S                        31
  56 +/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */
  57 +#define SCMI_SRST_T_WDT_S              32
  58 +#define SCMI_SRST_H_BOOTROM            33
  59 +#define SCMI_SRST_A_DCF                        34
  60 +#define SCMI_SRST_P_DCF                        35
  61 +#define SCMI_SRST_H_BOOTROM_NS         37
  62 +#define SCMI_SRST_P_KEYLADDER          46
  63 +#define SCMI_SRST_H_TRNG_S             47
  64 +/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */
  65 +#define SCMI_SRST_H_TRNG_NS            48
  66 +#define SCMI_SRST_D_SDMMC_BUFFER       49
  67 +#define SCMI_SRST_H_SDMMC              50
  68 +#define SCMI_SRST_H_SDMMC_BUFFER       51
  69 +#define SCMI_SRST_SDMMC                        52
  70 +#define SCMI_SRST_P_TRNG_CHK           53
  71 +#define SCMI_SRST_TRNG_S               54
  72 +
  73 +
  74  #endif