git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From db92246eeab5c5e3d42baac8da32c7d2e38238ef Mon Sep 17 00:00:00 2001
   2 From: Jonathan Bell <jonathan@raspberrypi.com>
   3 Date: Wed, 24 Jan 2024 13:55:45 +0000
   4 Subject: [PATCH 0889/1085] PCI: brcmstb: Enable CRS software visibility after
   5  linkup
   6
   7 It appears that bits in the Root Control Register are reset with
   8 perst_n, which means the PCI layer's call to enable CRS prior to
   9 adding/scanning the bus has no effect. Open-code the enable in
  10 brcm_pcie_start_link as a workaround.
  11
  12 Without CRS visibility, configuration reads issued by the CPU don't
  13 retire if the endpoint returns a CRS response - the RC will poll until a
  14 (large) timeout is reached. This means the core can stall for a long
  15 time during boot.
  16
  17 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  18 ---
  19  drivers/pci/controller/pcie-brcmstb.c | 12 +++++++++++-
  20  1 file changed, 11 insertions(+), 1 deletion(-)
  21
  22 --- a/drivers/pci/controller/pcie-brcmstb.c
  23 +++ b/drivers/pci/controller/pcie-brcmstb.c
  24 @@ -1385,7 +1385,7 @@ static int brcm_pcie_start_link(struct b
  25  {
  26         struct device *dev = pcie->dev;
  27         void __iomem *base = pcie->base;
  28 -       u16 nlw, cls, lnksta;
  29 +       u16 nlw, cls, lnksta, tmp16;
  30         bool ssc_good = false;
  31         int ret, i;
  32         u32 tmp;
  33 @@ -1449,6 +1449,16 @@ static int brcm_pcie_start_link(struct b
  34                  pci_speed_string(pcie_link_speed[cls]), nlw,
  35                  ssc_good ? "(SSC)" : "(!SSC)");
  36
  37 +       /*
  38 +        * RootCtl bits are reset by perst_n, which undoes pci_enable_crs()
  39 +        * called prior to pci_add_new_bus() during probe. Re-enable here.
  40 +        */
  41 +       tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCAP);
  42 +       if (tmp16 & PCI_EXP_RTCAP_CRSVIS) {
  43 +               tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL);
  44 +               u16p_replace_bits(&tmp16, 1, PCI_EXP_RTCTL_CRSSVE);
  45 +               writew(tmp16, base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL);
  46 +       }
  47         return 0;
  48  }
  49