git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From bf288bd25d6232310abb81db417376ce460eb032 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Thu, 27 Jun 2024 13:04:25 +0200
   4 Subject: [PATCH 3/4] clk: en7523: Remove PCIe reset open drain configuration
   5  for EN7581
   6
   7 PCIe reset open drain configuration will be managed by pinctrl driver.
   8
   9 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  11 Link: https://lore.kernel.org/r/43276af5f08a554b4ab2e52e8d437fff5c06a732.1719485847.git.lorenzo@kernel.org
  12 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  13 ---
  14  drivers/clk/clk-en7523.c | 12 ++----------
  15  1 file changed, 2 insertions(+), 10 deletions(-)
  16
  17 --- a/drivers/clk/clk-en7523.c
  18 +++ b/drivers/clk/clk-en7523.c
  19 @@ -37,8 +37,6 @@
  20  #define REG_PCIE1_MEM_MASK             0x0c
  21  #define REG_PCIE2_MEM                  0x10
  22  #define REG_PCIE2_MEM_MASK             0x14
  23 -#define REG_PCIE_RESET_OPEN_DRAIN      0x018c
  24 -#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
  25  #define REG_NP_SCU_PCIC                        0x88
  26  #define REG_NP_SCU_SSTR                        0x9c
  27  #define REG_PCIE_XSI0_SEL_MASK         GENMASK(14, 13)
  28 @@ -86,8 +84,7 @@ struct en_clk_soc_data {
  29                 const u16 *idx_map;
  30                 u16 idx_map_nr;
  31         } reset;
  32 -       int (*hw_init)(struct platform_device *pdev, void __iomem *base,
  33 -                      void __iomem *np_base);
  34 +       int (*hw_init)(struct platform_device *pdev, void __iomem *np_base);
  35  };
  36
  37  static const u32 gsw_base[] = { 400000000, 500000000 };
  38 @@ -416,7 +413,6 @@ static void en7581_pci_disable(struct cl
  39  }
  40
  41  static int en7581_clk_hw_init(struct platform_device *pdev,
  42 -                             void __iomem *base,
  43                               void __iomem *np_base)
  44  {
  45         void __iomem *pb_base;
  46 @@ -439,10 +435,6 @@ static int en7581_clk_hw_init(struct pla
  47         writel(0x28000000, pb_base + REG_PCIE2_MEM);
  48         writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
  49
  50 -       val = readl(base + REG_PCIE_RESET_OPEN_DRAIN);
  51 -       writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK,
  52 -              base + REG_PCIE_RESET_OPEN_DRAIN);
  53 -
  54         return 0;
  55  }
  56
  57 @@ -582,7 +574,7 @@ static int en7523_clk_probe(struct platf
  58
  59         soc_data = device_get_match_data(&pdev->dev);
  60         if (soc_data->hw_init) {
  61 -               r = soc_data->hw_init(pdev, base, np_base);
  62 +               r = soc_data->hw_init(pdev, np_base);
  63                 if (r)
  64                         return r;
  65         }