git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 494532921aacb496529d544fedfdb3a7b43dfef0 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Reichel <sebastian.reichel@collabora.com>
   3 Date: Tue, 9 Apr 2024 00:50:37 +0200
   4 Subject: [PATCH] arm64: dts: rockchip: add lower USB3 port to rock-5b
   5
   6 Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from
   7 Radxa Rock 5 Model B. The upper one is already supported.
   8
   9 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  10 Link: https://lore.kernel.org/r/20240408225109.128953-11-sebastian.reichel@collabora.com
  11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  12 ---
  13  arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++
  14  1 file changed, 17 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
  17 +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
  18 @@ -748,6 +748,14 @@
  19         status = "okay";
  20  };
  21
  22 +&u2phy1 {
  23 +       status = "okay";
  24 +};
  25 +
  26 +&u2phy1_otg {
  27 +       status = "okay";
  28 +};
  29 +
  30  &u2phy2 {
  31         status = "okay";
  32  };
  33 @@ -767,6 +775,10 @@
  34         status = "okay";
  35  };
  36
  37 +&usbdp_phy1 {
  38 +       status = "okay";
  39 +};
  40 +
  41  &usb_host0_ehci {
  42         status = "okay";
  43  };
  44 @@ -783,6 +795,11 @@
  45         status = "okay";
  46  };
  47
  48 +&usb_host1_xhci {
  49 +       dr_mode = "host";
  50 +       status = "okay";
  51 +};
  52 +
  53  &usb_host2_xhci {
  54         status = "okay";
  55  };