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1 From a79d2638a7150d1605fcadebb6baa36d27cdc48e Mon Sep 17 00:00:00 2001
2 From: Tim Harvey <tharvey@gateworks.com>
3 Date: Thu, 30 May 2024 10:21:45 -0700
4 Subject: [PATCH] arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support
5
6 The Gateworks GW82XX-2X is an ARM based single board computer (SBC)
7 comprised of the i.MX8M Plus based gw702x SoM and the gw82xx
8 baseboard featuring:
9 - i.MX8M Plus SoC
10 - LPDDR4 DRAM
11 - eMMC FLASH
12 - Gateworks System Controller (GSC)
13 - microSD (1.8V/3.3V Capable)
14 - panel status bi-color LED
15 - pushbutton switch
16 - fan controller with tachometer
17 - USB Type-C connector
18 - PCIe switch
19 - 2x GbE RJ45 connectors
20 - multi-protocol RS232/RS485/RS422 Serial ports
21 - 2x Flexible Socket Adapters with SDIO/UART/USB/PCIe
22 (for M.2 and miniPCIe expansion)
23 - 2x isolated CAN
24 - GPS
25 - accelerometer
26 - magnetometer
27 - off-board connectors for: SPI, GPIO, I2C, ADC
28 - Wide range DC power input
29 - support for 802.3at PoE (via adapter)
30
31 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
32 ---
33 .../devicetree/bindings/arm/fsl.yaml | 1 +
34 arch/arm64/boot/dts/freescale/Makefile | 1 +
35 .../dts/freescale/imx8mm-venice-gw82xx.dtsi | 460 +++++++++++++++
36 .../boot/dts/freescale/imx8mp-venice-gw82xx-2 | 19 +
37 .../dts/freescale/imx8mp-venice-gw82xx-2x.dts | 19 +
38 .../dts/freescale/imx8mp-venice-gw82xx.dtsi | 533 ++++++++++++++++++
39 6 files changed, 1033 insertions(+)
40 create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi
41 create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2
42 create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts
43 create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi
44
45 --- a/Documentation/devicetree/bindings/arm/fsl.yaml
46 +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
47 @@ -1037,6 +1037,7 @@ properties:
48 - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
49 - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
50 - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
51 + - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
52 - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
53 - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
54 - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
55 --- a/arch/arm64/boot/dts/freescale/Makefile
56 +++ b/arch/arm64/boot/dts/freescale/Makefile
57 @@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-
58 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb
59 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
60 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb
61 +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw82xx-2x.dtb
62 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
63 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
64 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb
65 --- /dev/null
66 +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw82xx.dtsi
67 @@ -0,0 +1,460 @@
68 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
69 +/*
70 + * Copyright 2020 Gateworks Corporation
71 + */
72 +
73 +#include <dt-bindings/gpio/gpio.h>
74 +#include <dt-bindings/leds/common.h>
75 +#include <dt-bindings/phy/phy-imx8-pcie.h>
76 +
77 +/ {
78 + aliases {
79 + ethernet1 = &eth1;
80 + usb0 = &usbotg1;
81 + usb1 = &usbotg2;
82 + };
83 +
84 + led-controller {
85 + compatible = "gpio-leds";
86 + pinctrl-names = "default";
87 + pinctrl-0 = <&pinctrl_gpio_leds>;
88 +
89 + led-0 {
90 + function = LED_FUNCTION_STATUS;
91 + color = <LED_COLOR_ID_GREEN>;
92 + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
93 + default-state = "on";
94 + linux,default-trigger = "heartbeat";
95 + };
96 +
97 + led-1 {
98 + function = LED_FUNCTION_STATUS;
99 + color = <LED_COLOR_ID_RED>;
100 + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
101 + default-state = "off";
102 + };
103 + };
104 +
105 + pcie0_refclk: pcie0-refclk {
106 + compatible = "fixed-clock";
107 + #clock-cells = <0>;
108 + clock-frequency = <100000000>;
109 + };
110 +
111 + pps {
112 + compatible = "pps-gpio";
113 + pinctrl-names = "default";
114 + pinctrl-0 = <&pinctrl_pps>;
115 + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
116 + status = "okay";
117 + };
118 +
119 + reg_1p8v: regulator-1p8v {
120 + compatible = "regulator-fixed";
121 + regulator-name = "1P8V";
122 + regulator-min-microvolt = <1800000>;
123 + regulator-max-microvolt = <1800000>;
124 + regulator-always-on;
125 + };
126 +
127 + reg_3p3v: regulator-3p3v {
128 + compatible = "regulator-fixed";
129 + regulator-name = "3P3V";
130 + regulator-min-microvolt = <3300000>;
131 + regulator-max-microvolt = <3300000>;
132 + regulator-always-on;
133 + };
134 +
135 + reg_usb_otg1_vbus: regulator-usb-otg1 {
136 + pinctrl-names = "default";
137 + pinctrl-0 = <&pinctrl_reg_usb1_en>;
138 + compatible = "regulator-fixed";
139 + regulator-name = "usb_otg1_vbus";
140 + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
141 + enable-active-high;
142 + regulator-min-microvolt = <5000000>;
143 + regulator-max-microvolt = <5000000>;
144 + };
145 +
146 + reg_usb_otg2_vbus: regulator-usb-otg2 {
147 + pinctrl-names = "default";
148 + pinctrl-0 = <&pinctrl_reg_usb2_en>;
149 + compatible = "regulator-fixed";
150 + regulator-name = "usb_otg2_vbus";
151 + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
152 + enable-active-high;
153 + regulator-min-microvolt = <5000000>;
154 + regulator-max-microvolt = <5000000>;
155 + };
156 +
157 + reg_wifi_en: regulator-wifi-en {
158 + pinctrl-names = "default";
159 + pinctrl-0 = <&pinctrl_reg_wl>;
160 + compatible = "regulator-fixed";
161 + regulator-name = "wl";
162 + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
163 + startup-delay-us = <100>;
164 + enable-active-high;
165 + regulator-min-microvolt = <3300000>;
166 + regulator-max-microvolt = <3300000>;
167 + };
168 +};
169 +
170 +/* off-board header */
171 +&ecspi2 {
172 + pinctrl-names = "default";
173 + pinctrl-0 = <&pinctrl_spi2>;
174 + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
175 + <&gpio1 10 GPIO_ACTIVE_LOW>;
176 + status = "okay";
177 +
178 + tpm@1 {
179 + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
180 + reg = <0x1>;
181 + spi-max-frequency = <36000000>;
182 + };
183 +};
184 +
185 +&gpio1 {
186 + gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
187 + "", "", "pci_usb_sel", "dio0",
188 + "", "dio1", "", "", "", "", "", "",
189 + "", "", "", "", "", "", "", "",
190 + "", "", "", "", "", "", "", "";
191 +};
192 +
193 +&gpio4 {
194 + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
195 + "mipi_gpio1", "", "", "pci_wdis#",
196 + "", "", "", "", "", "", "", "",
197 + "", "", "", "", "", "", "", "",
198 + "", "", "", "", "", "", "", "";
199 +};
200 +
201 +&i2c2 {
202 + clock-frequency = <400000>;
203 + pinctrl-names = "default";
204 + pinctrl-0 = <&pinctrl_i2c2>;
205 + status = "okay";
206 +
207 + accelerometer@19 {
208 + pinctrl-names = "default";
209 + pinctrl-0 = <&pinctrl_accel>;
210 + compatible = "st,lis2de12";
211 + reg = <0x19>;
212 + st,drdy-int-pin = <1>;
213 + interrupt-parent = <&gpio4>;
214 + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
215 + };
216 +
217 + // TODO: 0x6f PCIe switch
218 +};
219 +
220 +/* off-board header */
221 +// TODO: i2c expander
222 +&i2c3 {
223 + clock-frequency = <400000>;
224 + pinctrl-names = "default";
225 + pinctrl-0 = <&pinctrl_i2c3>;
226 + status = "okay";
227 +};
228 +
229 +&pcie_phy {
230 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
231 + fsl,clkreq-unsupported;
232 + clocks = <&pcie0_refclk>;
233 + clock-names = "ref";
234 + status = "okay";
235 +};
236 +
237 +&pcie0 {
238 + pinctrl-names = "default";
239 + pinctrl-0 = <&pinctrl_pcie0>;
240 + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
241 + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
242 + <&clk IMX8MM_CLK_PCIE1_AUX>;
243 + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
244 + <&clk IMX8MM_CLK_PCIE1_CTRL>;
245 + assigned-clock-rates = <10000000>, <250000000>;
246 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
247 + <&clk IMX8MM_SYS_PLL2_250M>;
248 + status = "okay";
249 +
250 + // TODO: this changes - new switch
251 + pcie@0,0 {
252 + reg = <0x0000 0 0 0 0>;
253 + device_type = "pci";
254 + #address-cells = <3>;
255 + #size-cells = <2>;
256 + ranges;
257 +
258 + pcie@0,0 {
259 + reg = <0x0000 0 0 0 0>;
260 + device_type = "pci";
261 + #address-cells = <3>;
262 + #size-cells = <2>;
263 + ranges;
264 +
265 + pcie@4,0 {
266 + reg = <0x2000 0 0 0 0>;
267 + device_type = "pci";
268 + #address-cells = <3>;
269 + #size-cells = <2>;
270 + ranges;
271 +
272 + eth1: ethernet@0,0 {
273 + reg = <0x0000 0 0 0 0>;
274 + #address-cells = <3>;
275 + #size-cells = <2>;
276 + ranges;
277 +
278 + local-mac-address = [00 00 00 00 00 00];
279 + };
280 + };
281 + };
282 + };
283 +};
284 +
285 +/* off-board header */
286 +&sai3 {
287 + pinctrl-names = "default";
288 + pinctrl-0 = <&pinctrl_sai3>;
289 + assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
290 + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
291 + assigned-clock-rates = <24576000>;
292 + status = "okay";
293 +};
294 +
295 +/* GPS */
296 +&uart1 {
297 + pinctrl-names = "default";
298 + pinctrl-0 = <&pinctrl_uart1>;
299 + status = "okay";
300 +};
301 +
302 +/* bluetooth HCI */
303 +&uart3 {
304 + pinctrl-names = "default";
305 + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
306 + cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
307 + rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
308 + status = "okay";
309 +
310 + bluetooth {
311 + compatible = "brcm,bcm4330-bt";
312 + shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
313 + };
314 +};
315 +
316 +/* RS232 */
317 +&uart4 {
318 + pinctrl-names = "default";
319 + pinctrl-0 = <&pinctrl_uart4>;
320 + status = "okay";
321 +};
322 +
323 +&usbotg1 {
324 + dr_mode = "otg";
325 + over-current-active-low;
326 + vbus-supply = <&reg_usb_otg1_vbus>;
327 + status = "okay";
328 +};
329 +
330 +&usbotg2 {
331 + dr_mode = "host";
332 + disable-over-current;
333 + vbus-supply = <&reg_usb_otg2_vbus>;
334 + status = "okay";
335 +};
336 +
337 +/* SDIO WiFi */
338 +&usdhc1 {
339 + pinctrl-names = "default";
340 + pinctrl-0 = <&pinctrl_usdhc1>;
341 + bus-width = <4>;
342 + non-removable;
343 + vmmc-supply = <&reg_wifi_en>;
344 + status = "okay";
345 +};
346 +
347 +/* microSD */
348 +&usdhc2 {
349 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
350 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
351 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
352 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
353 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
354 + bus-width = <4>;
355 + vmmc-supply = <&reg_3p3v>;
356 + status = "okay";
357 +};
358 +
359 +&iomuxc {
360 + pinctrl-names = "default";
361 + pinctrl-0 = <&pinctrl_hog>;
362 +
363 + pinctrl_hog: hoggrp {
364 + fsl,pins = <
365 + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
366 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
367 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
368 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
369 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
370 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
371 + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
372 + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
373 + >;
374 + };
375 +
376 + pinctrl_accel: accelgrp {
377 + fsl,pins = <
378 + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
379 + >;
380 + };
381 +
382 + pinctrl_bten: btengrp {
383 + fsl,pins = <
384 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
385 + >;
386 + };
387 +
388 + pinctrl_gpio_leds: gpioledgrp {
389 + fsl,pins = <
390 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
391 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
392 + >;
393 + };
394 +
395 + pinctrl_i2c3: i2c3grp {
396 + fsl,pins = <
397 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
398 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
399 + >;
400 + };
401 +
402 + pinctrl_pcie0: pcie0grp {
403 + fsl,pins = <
404 + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
405 + >;
406 + };
407 +
408 + pinctrl_pps: ppsgrp {
409 + fsl,pins = <
410 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
411 + >;
412 + };
413 +
414 + pinctrl_reg_wl: regwlgrp {
415 + fsl,pins = <
416 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
417 + >;
418 + };
419 +
420 + pinctrl_reg_usb1_en: regusb1grp {
421 + fsl,pins = <
422 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
423 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
424 + >;
425 + };
426 +
427 + pinctrl_reg_usb2_en: regusb2grp {
428 + fsl,pins = <
429 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
430 + >;
431 + };
432 +
433 + pinctrl_sai3: sai3grp {
434 + fsl,pins = <
435 + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
436 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
437 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
438 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
439 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
440 + >;
441 + };
442 +
443 + pinctrl_spi2: spi2grp {
444 + fsl,pins = <
445 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
446 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
447 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
448 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
449 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
450 + >;
451 + };
452 +
453 + pinctrl_uart1: uart1grp {
454 + fsl,pins = <
455 + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
456 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
457 + >;
458 + };
459 +
460 + pinctrl_uart3: uart3grp {
461 + fsl,pins = <
462 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
463 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
464 + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
465 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
466 + >;
467 + };
468 +
469 + pinctrl_uart4: uart4grp {
470 + fsl,pins = <
471 + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
472 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
473 + >;
474 + };
475 +
476 + pinctrl_usdhc1: usdhc1grp {
477 + fsl,pins = <
478 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
479 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
480 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
481 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
482 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
483 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
484 + >;
485 + };
486 +
487 + pinctrl_usdhc2: usdhc2grp {
488 + fsl,pins = <
489 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
490 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
491 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
492 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
493 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
494 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
495 + >;
496 + };
497 +
498 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
499 + fsl,pins = <
500 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
501 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
502 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
503 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
504 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
505 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
506 + >;
507 + };
508 +
509 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
510 + fsl,pins = <
511 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
512 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
513 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
514 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
515 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
516 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
517 + >;
518 + };
519 +
520 + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
521 + fsl,pins = <
522 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
523 + MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
524 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
525 + >;
526 + };
527 +};
528 --- /dev/null
529 +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2
530 @@ -0,0 +1,19 @@
531 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
532 +/*
533 + * Copyright 2024 Gateworks Corporation
534 + */
535 +
536 +/dts-v1/;
537 +
538 +#include "imx8mm.dtsi"
539 +#include "imx8mm-venice-gw700x.dtsi"
540 +#include "imx8mm-venice-gw82xx.dtsi"
541 +
542 +/ {
543 + model = "Gateworks Venice GW82xx-0x i.MX8MM Development Kit";
544 + compatible = "gw,imx8mm-gw82xx-0x", "fsl,imx8mm";
545 +
546 + chosen {
547 + stdout-path = &uart2;
548 + };
549 +};
550 --- /dev/null
551 +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts
552 @@ -0,0 +1,19 @@
553 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
554 +/*
555 + * Copyright 2024 Gateworks Corporation
556 + */
557 +
558 +/dts-v1/;
559 +
560 +#include "imx8mp.dtsi"
561 +#include "imx8mp-venice-gw702x.dtsi"
562 +#include "imx8mp-venice-gw82xx.dtsi"
563 +
564 +/ {
565 + model = "Gateworks Venice GW82xx-2x i.MX8MP Development Kit";
566 + compatible = "gateworks,imx8mp-gw82xx-2x", "fsl,imx8mp";
567 +
568 + chosen {
569 + stdout-path = &uart2;
570 + };
571 +};
572 --- /dev/null
573 +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi
574 @@ -0,0 +1,533 @@
575 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
576 +/*
577 + * Copyright 2024 Gateworks Corporation
578 + */
579 +
580 +#include <dt-bindings/gpio/gpio.h>
581 +#include <dt-bindings/leds/common.h>
582 +#include <dt-bindings/phy/phy-imx8-pcie.h>
583 +
584 +/ {
585 + aliases {
586 + ethernet1 = &eth1;
587 + fsa1 = &fsa0;
588 + fsa2 = &fsa1;
589 + };
590 +
591 + led-controller {
592 + compatible = "gpio-leds";
593 + pinctrl-names = "default";
594 + pinctrl-0 = <&pinctrl_gpio_leds>;
595 +
596 + led-0 {
597 + function = LED_FUNCTION_STATUS;
598 + color = <LED_COLOR_ID_GREEN>;
599 + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
600 + default-state = "on";
601 + linux,default-trigger = "heartbeat";
602 + };
603 +
604 + led-1 {
605 + function = LED_FUNCTION_STATUS;
606 + color = <LED_COLOR_ID_RED>;
607 + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
608 + default-state = "off";
609 + };
610 + };
611 +
612 + pcie0_refclk: clock-pcie0 {
613 + compatible = "fixed-clock";
614 + #clock-cells = <0>;
615 + clock-frequency = <100000000>;
616 + };
617 +
618 + pps {
619 + compatible = "pps-gpio";
620 + pinctrl-names = "default";
621 + pinctrl-0 = <&pinctrl_pps>;
622 + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
623 + };
624 +
625 + reg_usb2_vbus: regulator-usb2 {
626 + compatible = "regulator-fixed";
627 + pinctrl-names = "default";
628 + pinctrl-0 = <&pinctrl_reg_usb2_en>;
629 + regulator-name = "usb2_vbus";
630 + regulator-min-microvolt = <5000000>;
631 + regulator-max-microvolt = <5000000>;
632 + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
633 + enable-active-high;
634 + };
635 +
636 + reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
637 + compatible = "regulator-fixed";
638 + pinctrl-names = "default";
639 + pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
640 + regulator-name = "VDD_3V3_SD";
641 + regulator-max-microvolt = <3300000>;
642 + regulator-min-microvolt = <3300000>;
643 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
644 + enable-active-high;
645 + off-on-delay-us = <12000>;
646 + startup-delay-us = <100>;
647 + };
648 +};
649 +
650 +&ecspi2 {
651 + pinctrl-names = "default";
652 + pinctrl-0 = <&pinctrl_spi2>;
653 + cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>, /* CS0 onboard TPM */
654 + <&gpio5 13 GPIO_ACTIVE_LOW>, /* CS1 off-board J32 SPI */
655 + <&gpio1 12 GPIO_ACTIVE_LOW>, /* CS3 off-board J52 FSA1 */
656 + <&gpio4 26 GPIO_ACTIVE_LOW>; /* CS2 off-board J51 FSA2 */
657 + status = "okay";
658 +
659 + tpm@0 {
660 + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
661 + reg = <0x0>;
662 + spi-max-frequency = <10000000>;
663 + };
664 +};
665 +
666 +&flexcan1 {
667 + pinctrl-names = "default";
668 + pinctrl-0 = <&pinctrl_can1>;
669 + status = "okay";
670 +};
671 +
672 +&flexcan2 {
673 + pinctrl-names = "default";
674 + pinctrl-0 = <&pinctrl_can2>;
675 + status = "okay";
676 +};
677 +
678 +&gpio1 {
679 + gpio-line-names =
680 + "", "", "", "",
681 + "", "", "", "",
682 + "", "", "", "",
683 + "", "fsa2_gpio1", "", "",
684 + "", "", "", "",
685 + "", "", "", "",
686 + "", "", "", "",
687 + "", "", "", "";
688 +};
689 +
690 +&gpio4 {
691 + gpio-line-names =
692 + "", "", "", "",
693 + "", "", "", "",
694 + "dio1", "fsa1_gpio2", "", "dio0",
695 + "", "", "", "",
696 + "", "", "", "",
697 + "", "", "rs485_en", "rs485_term",
698 + "fsa2_gpio2", "fsa1_gpio1", "", "rs485_half",
699 + "", "", "", "";
700 +};
701 +
702 +&i2c2 {
703 + accelerometer@19 {
704 + compatible = "st,lis2de12";
705 + reg = <0x19>;
706 + pinctrl-names = "default";
707 + pinctrl-0 = <&pinctrl_accel>;
708 + interrupt-parent = <&gpio4>;
709 + interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
710 + st,drdy-int-pin = <1>;
711 + };
712 +
713 + magnetometer@1e {
714 + compatible = "st,lis2mdl";
715 + reg = <0x1e>;
716 + pinctrl-names = "default";
717 + pinctrl-0 = <&pinctrl_mag>;
718 + interrupt-parent = <&gpio4>;
719 + interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
720 + };
721 +};
722 +
723 +&i2c3 {
724 + i2c-mux@70 {
725 + compatible = "nxp,pca9548";
726 + reg = <0x70>;
727 + #address-cells = <1>;
728 + #size-cells = <0>;
729 +
730 + /* J30 */
731 + fsa1: i2c@0 {
732 + reg = <0>;
733 + pinctrl-names = "default";
734 + pinctrl-0 = <&pinctrl_fsa2i2c>;
735 + #address-cells = <1>;
736 + #size-cells = <0>;
737 +
738 + gpio@20 {
739 + compatible = "nxp,pca9555";
740 + reg = <0x20>;
741 + interrupt-parent = <&gpio4>;
742 + interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
743 + interrupt-controller;
744 + #interrupt-cells = <2>;
745 + gpio-controller;
746 + #gpio-cells = <2>;
747 + };
748 +
749 + eeprom@54 {
750 + compatible = "atmel,24c02";
751 + reg = <0x54>;
752 + pagesize = <16>;
753 + };
754 +
755 + eeprom@55 {
756 + compatible = "atmel,24c02";
757 + reg = <0x55>;
758 + pagesize = <16>;
759 + };
760 + };
761 +
762 + /* J29 */
763 + fsa0: i2c@1 {
764 + reg = <1>;
765 + pinctrl-names = "default";
766 + pinctrl-0 = <&pinctrl_fsa1i2c>;
767 + #address-cells = <1>;
768 + #size-cells = <0>;
769 +
770 + gpio@20 {
771 + compatible = "nxp,pca9555";
772 + reg = <0x20>;
773 + interrupt-parent = <&gpio4>;
774 + interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
775 + interrupt-controller;
776 + #interrupt-cells = <2>;
777 + gpio-controller;
778 + #gpio-cells = <2>;
779 + };
780 +
781 + eeprom@54 {
782 + compatible = "atmel,24c02";
783 + reg = <0x54>;
784 + pagesize = <16>;
785 + };
786 +
787 + eeprom@55 {
788 + compatible = "atmel,24c02";
789 + reg = <0x55>;
790 + pagesize = <16>;
791 + };
792 + };
793 +
794 + /* J33 */
795 + i2c@2 {
796 + reg = <2>;
797 + #address-cells = <1>;
798 + #size-cells = <0>;
799 + };
800 + };
801 +};
802 +
803 +&pcie_phy {
804 + clocks = <&pcie0_refclk>;
805 + clock-names = "ref";
806 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
807 + fsl,clkreq-unsupported;
808 + status = "okay";
809 +};
810 +
811 +&pcie {
812 + pinctrl-names = "default";
813 + pinctrl-0 = <&pinctrl_pcie0>;
814 + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
815 + status = "okay";
816 +
817 + pcie@0,0 {
818 + reg = <0x0000 0 0 0 0>;
819 + device_type = "pci";
820 + #address-cells = <3>;
821 + #size-cells = <2>;
822 + ranges;
823 +
824 + pcie@0,0 {
825 + reg = <0x0000 0 0 0 0>;
826 + device_type = "pci";
827 + #address-cells = <3>;
828 + #size-cells = <2>;
829 + ranges;
830 +
831 + pcie@7,0 {
832 + reg = <0x3800 0 0 0 0>;
833 + device_type = "pci";
834 + #address-cells = <3>;
835 + #size-cells = <2>;
836 + ranges;
837 +
838 + eth1: ethernet@0,0 {
839 + reg = <0x0000 0 0 0 0>;
840 + #address-cells = <3>;
841 + #size-cells = <2>;
842 + ranges;
843 + local-mac-address = [00 00 00 00 00 00];
844 + };
845 + };
846 + };
847 + };
848 +};
849 +
850 +/* GPS */
851 +&uart1 {
852 + pinctrl-names = "default";
853 + pinctrl-0 = <&pinctrl_uart1>;
854 + status = "okay";
855 +};
856 +
857 +/* RS232 */
858 +&uart4 {
859 + pinctrl-names = "default";
860 + pinctrl-0 = <&pinctrl_uart4>;
861 + status = "okay";
862 +};
863 +
864 +/* USB1 - FSA1 */
865 +&usb3_0 {
866 + fsl,permanently-attached;
867 + fsl,disable-port-power-control;
868 + status = "okay";
869 +};
870 +
871 +&usb3_phy0 {
872 + status = "okay";
873 +};
874 +
875 +&usb_dwc3_0 {
876 + dr_mode = "host";
877 + status = "okay";
878 +};
879 +
880 +/* USB2 - USB3.0 Hub */
881 +&usb3_1 {
882 + fsl,permanently-attached;
883 + fsl,disable-port-power-control;
884 + status = "okay";
885 +};
886 +
887 +&usb3_phy1 {
888 + vbus-supply = <&reg_usb2_vbus>;
889 + status = "okay";
890 +};
891 +
892 +&usb_dwc3_1 {
893 + dr_mode = "host";
894 + status = "okay";
895 +};
896 +
897 +/* SDIO 1.8V */
898 +&usdhc1 {
899 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
900 + pinctrl-0 = <&pinctrl_usdhc1>;
901 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
902 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
903 + bus-width = <4>;
904 + non-removable;
905 + status = "okay";
906 +};
907 +
908 +/* microSD */
909 +&usdhc2 {
910 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
911 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
912 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
913 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
914 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; /* CD is active high */
915 + bus-width = <4>;
916 + vmmc-supply = <&reg_usdhc2_vmmc>;
917 + status = "okay";
918 +};
919 +
920 +&iomuxc {
921 + pinctrl-names = "default";
922 + pinctrl-0 = <&pinctrl_hog>;
923 +
924 + pinctrl_hog: hoggrp {
925 + fsl,pins = <
926 + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
927 + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
928 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
929 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
930 + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
931 + >;
932 + };
933 +
934 + pinctrl_accel: accelgrp {
935 + fsl,pins = <
936 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ# */
937 + >;
938 + };
939 +
940 + pinctrl_can1: can1grp {
941 + fsl,pins = <
942 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
943 + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
944 + >;
945 + };
946 +
947 + pinctrl_can2: can2grp {
948 + fsl,pins = <
949 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
950 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
951 + >;
952 + };
953 +
954 + pinctrl_gpio_leds: gpioledgrp {
955 + fsl,pins = <
956 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
957 + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
958 + >;
959 + };
960 +
961 + pinctrl_fsa1i2c: fsa1i2cgrp {
962 + fsl,pins = <
963 + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1d0 /* FSA1_ALERT# */
964 + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x400001d0 /* FSA1_GPIO1 */
965 + MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x400001d0 /* FSA1_GPIO2 */
966 + >;
967 + };
968 +
969 + pinctrl_fsa2i2c: fsa2i2cgrp {
970 + fsl,pins = <
971 + MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x1d0 /* FSA2_ALERT# */
972 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x400001d0 /* FSA2_GPIO1 */
973 + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x400001d0 /* FSA2_GPIO2 */
974 + >;
975 + };
976 +
977 + pinctrl_mag: maggrp {
978 + fsl,pins = <
979 + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x140 /* IRQ# */
980 + >;
981 + };
982 +
983 + pinctrl_pcie0: pcie0grp {
984 + fsl,pins = <
985 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 /* PERST# */
986 + >;
987 + };
988 +
989 + pinctrl_pps: ppsgrp {
990 + fsl,pins = <
991 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
992 + >;
993 + };
994 +
995 + pinctrl_reg_usb2_en: regusb2grp {
996 + fsl,pins = <
997 + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
998 + >;
999 + };
1000 +
1001 + pinctrl_spi2: spi2grp {
1002 + fsl,pins = <
1003 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0xd0
1004 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0xd0
1005 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0xd0
1006 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 /* J32_CS */
1007 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* TPM_CS */
1008 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 /* FSA1_CS */
1009 + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x140 /* FSA2_CS */
1010 + >;
1011 + };
1012 +
1013 + pinctrl_uart1: uart1grp {
1014 + fsl,pins = <
1015 + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
1016 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
1017 + >;
1018 + };
1019 +
1020 + pinctrl_uart4: uart4grp {
1021 + fsl,pins = <
1022 + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
1023 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
1024 + >;
1025 + };
1026 +
1027 + pinctrl_usdhc1: usdhc1grp {
1028 + fsl,pins = <
1029 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1030 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1031 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1032 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1033 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1034 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1035 + >;
1036 + };
1037 +
1038 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1039 + fsl,pins = <
1040 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
1041 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
1042 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
1043 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
1044 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
1045 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
1046 + >;
1047 + };
1048 +
1049 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1050 + fsl,pins = <
1051 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
1052 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
1053 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
1054 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
1055 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
1056 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
1057 + >;
1058 + };
1059 +
1060 + pinctrl_usdhc2: usdhc2grp {
1061 + fsl,pins = <
1062 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
1063 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
1064 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
1065 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
1066 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
1067 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
1068 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1069 + >;
1070 + };
1071 +
1072 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1073 + fsl,pins = <
1074 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
1075 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
1076 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
1077 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
1078 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
1079 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
1080 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1081 + >;
1082 + };
1083 +
1084 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1085 + fsl,pins = <
1086 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
1087 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
1088 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
1089 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
1090 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
1091 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
1092 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
1093 + >;
1094 + };
1095 +
1096 + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
1097 + fsl,pins = <
1098 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1d0
1099 + >;
1100 + };
1101 +
1102 + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
1103 + fsl,pins = <
1104 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
1105 + >;
1106 + };
1107 +};
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