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1 From 4c452f7ea86212934ae896842847d1671e13a18b Mon Sep 17 00:00:00 2001
2 From: "SkyLake.Huang" <skylake.huang@mediatek.com>
3 Date: Sat, 9 Nov 2024 00:34:51 +0800
4 Subject: [PATCH] net: phy: mediatek: Re-organize MediaTek ethernet phy drivers
5
6 Re-organize MediaTek ethernet phy driver files and get ready to integrate
7 some common functions and add new 2.5G phy driver.
8 mtk-ge.c: MT7530 Gphy on MT7621 & MT7531 Gphy
9 mtk-ge-soc.c: Built-in Gphy on MT7981 & Built-in switch Gphy on MT7988
10 mtk-2p5ge.c: Planned for built-in 2.5G phy on MT7988
11
12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
13 Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
14 Signed-off-by: David S. Miller <davem@davemloft.net>
15 ---
16 MAINTAINERS | 4 ++--
17 drivers/net/phy/Kconfig | 17 +-------------
18 drivers/net/phy/Makefile | 3 +--
19 drivers/net/phy/mediatek/Kconfig | 22 +++++++++++++++++++
20 drivers/net/phy/mediatek/Makefile | 3 +++
21 .../mtk-ge-soc.c} | 0
22 .../phy/{mediatek-ge.c => mediatek/mtk-ge.c} | 0
23 7 files changed, 29 insertions(+), 20 deletions(-)
24 create mode 100644 drivers/net/phy/mediatek/Kconfig
25 create mode 100644 drivers/net/phy/mediatek/Makefile
26 rename drivers/net/phy/{mediatek-ge-soc.c => mediatek/mtk-ge-soc.c} (100%)
27 rename drivers/net/phy/{mediatek-ge.c => mediatek/mtk-ge.c} (100%)
28
29 --- a/drivers/net/phy/Kconfig
30 +++ b/drivers/net/phy/Kconfig
31 @@ -234,22 +234,7 @@ config MAXLINEAR_GPHY
32 Support for the Maxlinear GPY115, GPY211, GPY212, GPY215,
33 GPY241, GPY245 PHYs.
34
35 -config MEDIATEK_GE_PHY
36 - tristate "MediaTek Gigabit Ethernet PHYs"
37 - help
38 - Supports the MediaTek Gigabit Ethernet PHYs.
39 -
40 -config MEDIATEK_GE_SOC_PHY
41 - tristate "MediaTek SoC Ethernet PHYs"
42 - depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
43 - depends on NVMEM_MTK_EFUSE
44 - help
45 - Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
46 -
47 - Include support for built-in Ethernet PHYs which are present in
48 - the MT7981 and MT7988 SoCs. These PHYs need calibration data
49 - present in the SoCs efuse and will dynamically calibrate VCM
50 - (common-mode voltage) during startup.
51 +source "drivers/net/phy/mediatek/Kconfig"
52
53 config MICREL_PHY
54 tristate "Micrel PHYs"
55 --- a/drivers/net/phy/Makefile
56 +++ b/drivers/net/phy/Makefile
57 @@ -66,8 +66,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
58 obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o
59 obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
60 obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
61 -obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
62 -obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
63 +obj-y += mediatek/
64 obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
65 obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
66 obj-$(CONFIG_MICREL_PHY) += micrel.o
67 --- /dev/null
68 +++ b/drivers/net/phy/mediatek/Kconfig
69 @@ -0,0 +1,22 @@
70 +# SPDX-License-Identifier: GPL-2.0-only
71 +config MEDIATEK_GE_PHY
72 + tristate "MediaTek Gigabit Ethernet PHYs"
73 + help
74 + Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
75 +
76 + Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531.
77 + You may find mt7530 inside mt7621. This driver shares some
78 + common operations with MediaTek SoC built-in Gigabit
79 + Ethernet PHYs.
80 +
81 +config MEDIATEK_GE_SOC_PHY
82 + tristate "MediaTek SoC Ethernet PHYs"
83 + depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
84 + depends on NVMEM_MTK_EFUSE
85 + help
86 + Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
87 +
88 + Include support for built-in Ethernet PHYs which are present in
89 + the MT7981 and MT7988 SoCs. These PHYs need calibration data
90 + present in the SoCs efuse and will dynamically calibrate VCM
91 + (common-mode voltage) during startup.
92 --- /dev/null
93 +++ b/drivers/net/phy/mediatek/Makefile
94 @@ -0,0 +1,3 @@
95 +# SPDX-License-Identifier: GPL-2.0
96 +obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
97 +obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o
98 --- a/drivers/net/phy/mediatek-ge-soc.c
99 +++ /dev/null
100 @@ -1,1610 +0,0 @@
101 -// SPDX-License-Identifier: GPL-2.0+
102 -#include <linux/bitfield.h>
103 -#include <linux/bitmap.h>
104 -#include <linux/mfd/syscon.h>
105 -#include <linux/module.h>
106 -#include <linux/nvmem-consumer.h>
107 -#include <linux/pinctrl/consumer.h>
108 -#include <linux/phy.h>
109 -#include <linux/regmap.h>
110 -
111 -#define MTK_GPHY_ID_MT7981 0x03a29461
112 -#define MTK_GPHY_ID_MT7988 0x03a29481
113 -
114 -#define MTK_EXT_PAGE_ACCESS 0x1f
115 -#define MTK_PHY_PAGE_STANDARD 0x0000
116 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003
117 -
118 -#define MTK_PHY_LPI_REG_14 0x14
119 -#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
120 -
121 -#define MTK_PHY_LPI_REG_1c 0x1c
122 -#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
123 -
124 -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
125 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
126 -
127 -#define ANALOG_INTERNAL_OPERATION_MAX_US 20
128 -#define TXRESERVE_MIN 0
129 -#define TXRESERVE_MAX 7
130 -
131 -#define MTK_PHY_ANARG_RG 0x10
132 -#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
133 -
134 -/* Registers on MDIO_MMD_VEND1 */
135 -#define MTK_PHY_TXVLD_DA_RG 0x12
136 -#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
137 -#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
138 -
139 -#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
140 -#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
141 -#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
142 -
143 -#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
144 -#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
145 -#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
146 -
147 -#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
148 -#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
149 -#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
150 -
151 -#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
152 -#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
153 -#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
154 -
155 -#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
156 -#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
157 -#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
158 -
159 -#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
160 -#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
161 -#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
162 -
163 -#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
164 -#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
165 -#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
166 -
167 -#define MTK_PHY_RXADC_CTRL_RG7 0xc6
168 -#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
169 -
170 -#define MTK_PHY_RXADC_CTRL_RG9 0xc8
171 -#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
172 -#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
173 -#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
174 -#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
175 -
176 -#define MTK_PHY_LDO_OUTPUT_V 0xd7
177 -
178 -#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
179 -#define MTK_PHY_RG_CAL_CKINV BIT(12)
180 -#define MTK_PHY_RG_ANA_CALEN BIT(8)
181 -#define MTK_PHY_RG_ZCALEN_A BIT(0)
182 -
183 -#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
184 -#define MTK_PHY_RG_ZCALEN_B BIT(12)
185 -#define MTK_PHY_RG_ZCALEN_C BIT(8)
186 -#define MTK_PHY_RG_ZCALEN_D BIT(4)
187 -#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
188 -
189 -#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
190 -#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
191 -
192 -#define MTK_PHY_RG_TX_FILTER 0xfe
193 -
194 -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
195 -#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
196 -#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
197 -
198 -#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
199 -#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
200 -
201 -#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
202 -#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
203 -
204 -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
205 -#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
206 -#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
207 -
208 -#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
209 -#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
210 -#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
211 -
212 -#define MTK_PHY_RG_AD_CAL_COMP 0x17a
213 -#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
214 -
215 -#define MTK_PHY_RG_AD_CAL_CLK 0x17b
216 -#define MTK_PHY_DA_CAL_CLK BIT(0)
217 -
218 -#define MTK_PHY_RG_AD_CALIN 0x17c
219 -#define MTK_PHY_DA_CALIN_FLAG BIT(0)
220 -
221 -#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
222 -#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
223 -
224 -#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
225 -#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
226 -
227 -#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
228 -#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
229 -
230 -#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
231 -#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
232 -
233 -#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
234 -#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
235 -
236 -#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
237 -#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
238 -
239 -#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
240 -#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
241 -
242 -#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
243 -#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
244 -
245 -#define MTK_PHY_RG_DEV1E_REG19b 0x19b
246 -#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
247 -
248 -#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
249 -#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
250 -#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
251 -#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
252 -#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
253 -#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
254 -#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
255 -#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
256 -#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
257 -#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
258 -
259 -#define MTK_PHY_RG_DEV1E_REG234 0x234
260 -#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
261 -#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
262 -#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
263 -
264 -#define MTK_PHY_RG_LPF_CNT_VAL 0x235
265 -
266 -#define MTK_PHY_RG_DEV1E_REG238 0x238
267 -#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
268 -#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
269 -
270 -#define MTK_PHY_RG_DEV1E_REG239 0x239
271 -#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
272 -#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
273 -
274 -#define MTK_PHY_RG_DEV1E_REG27C 0x27c
275 -#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
276 -#define MTK_PHY_RG_DEV1E_REG27D 0x27d
277 -#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
278 -
279 -#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
280 -#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
281 -#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
282 -
283 -#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
284 -#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
285 -#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
286 -#define MTK_PHY_LPI_TR_READY BIT(9)
287 -#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
288 -
289 -#define MTK_PHY_RG_DEV1E_REG323 0x323
290 -#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
291 -#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
292 -
293 -#define MTK_PHY_RG_DEV1E_REG324 0x324
294 -#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
295 -#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
296 -
297 -#define MTK_PHY_RG_DEV1E_REG326 0x326
298 -#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
299 -#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
300 -#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
301 -#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
302 -#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
303 -
304 -#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
305 -#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
306 -
307 -#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
308 -#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
309 -#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
310 -#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
311 -
312 -/* Registers on MDIO_MMD_VEND2 */
313 -#define MTK_PHY_LED0_ON_CTRL 0x24
314 -#define MTK_PHY_LED1_ON_CTRL 0x26
315 -#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
316 -#define MTK_PHY_LED_ON_LINK1000 BIT(0)
317 -#define MTK_PHY_LED_ON_LINK100 BIT(1)
318 -#define MTK_PHY_LED_ON_LINK10 BIT(2)
319 -#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
320 - MTK_PHY_LED_ON_LINK100 |\
321 - MTK_PHY_LED_ON_LINK1000)
322 -#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
323 -#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
324 -#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
325 -#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
326 -#define MTK_PHY_LED_ON_POLARITY BIT(14)
327 -#define MTK_PHY_LED_ON_ENABLE BIT(15)
328 -
329 -#define MTK_PHY_LED0_BLINK_CTRL 0x25
330 -#define MTK_PHY_LED1_BLINK_CTRL 0x27
331 -#define MTK_PHY_LED_BLINK_1000TX BIT(0)
332 -#define MTK_PHY_LED_BLINK_1000RX BIT(1)
333 -#define MTK_PHY_LED_BLINK_100TX BIT(2)
334 -#define MTK_PHY_LED_BLINK_100RX BIT(3)
335 -#define MTK_PHY_LED_BLINK_10TX BIT(4)
336 -#define MTK_PHY_LED_BLINK_10RX BIT(5)
337 -#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
338 - MTK_PHY_LED_BLINK_100RX |\
339 - MTK_PHY_LED_BLINK_1000RX)
340 -#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
341 - MTK_PHY_LED_BLINK_100TX |\
342 - MTK_PHY_LED_BLINK_1000TX)
343 -#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
344 -#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
345 -#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
346 -#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
347 -
348 -#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
349 -
350 -#define MTK_PHY_RG_BG_RASEL 0x115
351 -#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
352 -
353 -/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
354 -#define RG_GPIO_MISC_TPBANK0 0x6f0
355 -#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
356 -
357 -/* These macro privides efuse parsing for internal phy. */
358 -#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
359 -#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
360 -#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
361 -#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
362 -#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
363 -
364 -#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
365 -#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
366 -#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
367 -#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
368 -#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
369 -
370 -#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
371 -#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
372 -
373 -#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
374 -#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
375 -
376 -enum {
377 - NO_PAIR,
378 - PAIR_A,
379 - PAIR_B,
380 - PAIR_C,
381 - PAIR_D,
382 -};
383 -
384 -enum calibration_mode {
385 - EFUSE_K,
386 - SW_K
387 -};
388 -
389 -enum CAL_ITEM {
390 - REXT,
391 - TX_OFFSET,
392 - TX_AMP,
393 - TX_R50,
394 - TX_VCM
395 -};
396 -
397 -enum CAL_MODE {
398 - EFUSE_M,
399 - SW_M
400 -};
401 -
402 -#define MTK_PHY_LED_STATE_FORCE_ON 0
403 -#define MTK_PHY_LED_STATE_FORCE_BLINK 1
404 -#define MTK_PHY_LED_STATE_NETDEV 2
405 -
406 -struct mtk_socphy_priv {
407 - unsigned long led_state;
408 -};
409 -
410 -struct mtk_socphy_shared {
411 - u32 boottrap;
412 - struct mtk_socphy_priv priv[4];
413 -};
414 -
415 -static int mtk_socphy_read_page(struct phy_device *phydev)
416 -{
417 - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
418 -}
419 -
420 -static int mtk_socphy_write_page(struct phy_device *phydev, int page)
421 -{
422 - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
423 -}
424 -
425 -/* One calibration cycle consists of:
426 - * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
427 - * until AD_CAL_COMP is ready to output calibration result.
428 - * 2.Wait until DA_CAL_CLK is available.
429 - * 3.Fetch AD_CAL_COMP_OUT.
430 - */
431 -static int cal_cycle(struct phy_device *phydev, int devad,
432 - u32 regnum, u16 mask, u16 cal_val)
433 -{
434 - int reg_val;
435 - int ret;
436 -
437 - phy_modify_mmd(phydev, devad, regnum,
438 - mask, cal_val);
439 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
440 - MTK_PHY_DA_CALIN_FLAG);
441 -
442 - ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
443 - MTK_PHY_RG_AD_CAL_CLK, reg_val,
444 - reg_val & MTK_PHY_DA_CAL_CLK, 500,
445 - ANALOG_INTERNAL_OPERATION_MAX_US,
446 - false);
447 - if (ret) {
448 - phydev_err(phydev, "Calibration cycle timeout\n");
449 - return ret;
450 - }
451 -
452 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
453 - MTK_PHY_DA_CALIN_FLAG);
454 - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
455 - if (ret < 0)
456 - return ret;
457 - ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
458 - phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
459 -
460 - return ret;
461 -}
462 -
463 -static int rext_fill_result(struct phy_device *phydev, u16 *buf)
464 -{
465 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
466 - MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
467 - phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
468 - MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
469 -
470 - return 0;
471 -}
472 -
473 -static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
474 -{
475 - u16 rext_cal_val[2];
476 -
477 - rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
478 - rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
479 - rext_fill_result(phydev, rext_cal_val);
480 -
481 - return 0;
482 -}
483 -
484 -static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
485 -{
486 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
487 - MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
488 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
489 - MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
490 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
491 - MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
492 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
493 - MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
494 -
495 - return 0;
496 -}
497 -
498 -static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
499 -{
500 - u16 tx_offset_cal_val[4];
501 -
502 - tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
503 - tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
504 - tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
505 - tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
506 -
507 - tx_offset_fill_result(phydev, tx_offset_cal_val);
508 -
509 - return 0;
510 -}
511 -
512 -static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
513 -{
514 - const int vals_9481[16] = { 10, 6, 6, 10,
515 - 10, 6, 6, 10,
516 - 10, 6, 6, 10,
517 - 10, 6, 6, 10 };
518 - const int vals_9461[16] = { 7, 1, 4, 7,
519 - 7, 1, 4, 7,
520 - 7, 1, 4, 7,
521 - 7, 1, 4, 7 };
522 - int bias[16] = {};
523 - int i;
524 -
525 - switch (phydev->drv->phy_id) {
526 - case MTK_GPHY_ID_MT7981:
527 - /* We add some calibration to efuse values
528 - * due to board level influence.
529 - * GBE: +7, TBT: +1, HBT: +4, TST: +7
530 - */
531 - memcpy(bias, (const void *)vals_9461, sizeof(bias));
532 - break;
533 - case MTK_GPHY_ID_MT7988:
534 - memcpy(bias, (const void *)vals_9481, sizeof(bias));
535 - break;
536 - }
537 -
538 - /* Prevent overflow */
539 - for (i = 0; i < 12; i++) {
540 - if (buf[i >> 2] + bias[i] > 63) {
541 - buf[i >> 2] = 63;
542 - bias[i] = 0;
543 - }
544 - }
545 -
546 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
547 - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
548 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
549 - buf[0] + bias[0]));
550 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
551 - MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
552 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
553 - buf[0] + bias[1]));
554 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
555 - MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
556 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
557 - buf[0] + bias[2]));
558 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
559 - MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
560 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
561 - buf[0] + bias[3]));
562 -
563 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
564 - MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
565 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
566 - buf[1] + bias[4]));
567 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
568 - MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
569 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
570 - buf[1] + bias[5]));
571 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
572 - MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
573 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
574 - buf[1] + bias[6]));
575 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
576 - MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
577 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
578 - buf[1] + bias[7]));
579 -
580 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
581 - MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
582 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
583 - buf[2] + bias[8]));
584 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
585 - MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
586 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
587 - buf[2] + bias[9]));
588 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
589 - MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
590 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
591 - buf[2] + bias[10]));
592 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
593 - MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
594 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
595 - buf[2] + bias[11]));
596 -
597 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
598 - MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
599 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
600 - buf[3] + bias[12]));
601 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
602 - MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
603 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
604 - buf[3] + bias[13]));
605 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
606 - MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
607 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
608 - buf[3] + bias[14]));
609 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
610 - MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
611 - FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
612 - buf[3] + bias[15]));
613 -
614 - return 0;
615 -}
616 -
617 -static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
618 -{
619 - u16 tx_amp_cal_val[4];
620 -
621 - tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
622 - tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
623 - tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
624 - tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
625 - tx_amp_fill_result(phydev, tx_amp_cal_val);
626 -
627 - return 0;
628 -}
629 -
630 -static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
631 - u8 txg_calen_x)
632 -{
633 - int bias = 0;
634 - u16 reg, val;
635 -
636 - if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
637 - bias = -1;
638 -
639 - val = clamp_val(bias + tx_r50_cal_val, 0, 63);
640 -
641 - switch (txg_calen_x) {
642 - case PAIR_A:
643 - reg = MTK_PHY_DA_TX_R50_PAIR_A;
644 - break;
645 - case PAIR_B:
646 - reg = MTK_PHY_DA_TX_R50_PAIR_B;
647 - break;
648 - case PAIR_C:
649 - reg = MTK_PHY_DA_TX_R50_PAIR_C;
650 - break;
651 - case PAIR_D:
652 - reg = MTK_PHY_DA_TX_R50_PAIR_D;
653 - break;
654 - default:
655 - return -EINVAL;
656 - }
657 -
658 - phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
659 -
660 - return 0;
661 -}
662 -
663 -static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
664 - u8 txg_calen_x)
665 -{
666 - u16 tx_r50_cal_val;
667 -
668 - switch (txg_calen_x) {
669 - case PAIR_A:
670 - tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
671 - break;
672 - case PAIR_B:
673 - tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
674 - break;
675 - case PAIR_C:
676 - tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
677 - break;
678 - case PAIR_D:
679 - tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
680 - break;
681 - default:
682 - return -EINVAL;
683 - }
684 - tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
685 -
686 - return 0;
687 -}
688 -
689 -static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
690 -{
691 - u8 lower_idx, upper_idx, txreserve_val;
692 - u8 lower_ret, upper_ret;
693 - int ret;
694 -
695 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
696 - MTK_PHY_RG_ANA_CALEN);
697 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
698 - MTK_PHY_RG_CAL_CKINV);
699 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
700 - MTK_PHY_RG_TXVOS_CALEN);
701 -
702 - switch (rg_txreserve_x) {
703 - case PAIR_A:
704 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
705 - MTK_PHY_RG_DASN_DAC_IN0_A,
706 - MTK_PHY_DASN_DAC_IN0_A_MASK);
707 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
708 - MTK_PHY_RG_DASN_DAC_IN1_A,
709 - MTK_PHY_DASN_DAC_IN1_A_MASK);
710 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
711 - MTK_PHY_RG_ANA_CAL_RG0,
712 - MTK_PHY_RG_ZCALEN_A);
713 - break;
714 - case PAIR_B:
715 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
716 - MTK_PHY_RG_DASN_DAC_IN0_B,
717 - MTK_PHY_DASN_DAC_IN0_B_MASK);
718 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
719 - MTK_PHY_RG_DASN_DAC_IN1_B,
720 - MTK_PHY_DASN_DAC_IN1_B_MASK);
721 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
722 - MTK_PHY_RG_ANA_CAL_RG1,
723 - MTK_PHY_RG_ZCALEN_B);
724 - break;
725 - case PAIR_C:
726 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
727 - MTK_PHY_RG_DASN_DAC_IN0_C,
728 - MTK_PHY_DASN_DAC_IN0_C_MASK);
729 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
730 - MTK_PHY_RG_DASN_DAC_IN1_C,
731 - MTK_PHY_DASN_DAC_IN1_C_MASK);
732 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
733 - MTK_PHY_RG_ANA_CAL_RG1,
734 - MTK_PHY_RG_ZCALEN_C);
735 - break;
736 - case PAIR_D:
737 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
738 - MTK_PHY_RG_DASN_DAC_IN0_D,
739 - MTK_PHY_DASN_DAC_IN0_D_MASK);
740 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
741 - MTK_PHY_RG_DASN_DAC_IN1_D,
742 - MTK_PHY_DASN_DAC_IN1_D_MASK);
743 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
744 - MTK_PHY_RG_ANA_CAL_RG1,
745 - MTK_PHY_RG_ZCALEN_D);
746 - break;
747 - default:
748 - ret = -EINVAL;
749 - goto restore;
750 - }
751 -
752 - lower_idx = TXRESERVE_MIN;
753 - upper_idx = TXRESERVE_MAX;
754 -
755 - phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
756 - while ((upper_idx - lower_idx) > 1) {
757 - txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
758 - ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
759 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
760 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
761 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
762 - MTK_PHY_DA_RX_PSBN_LP_MASK,
763 - txreserve_val << 12 | txreserve_val << 8 |
764 - txreserve_val << 4 | txreserve_val);
765 - if (ret == 1) {
766 - upper_idx = txreserve_val;
767 - upper_ret = ret;
768 - } else if (ret == 0) {
769 - lower_idx = txreserve_val;
770 - lower_ret = ret;
771 - } else {
772 - goto restore;
773 - }
774 - }
775 -
776 - if (lower_idx == TXRESERVE_MIN) {
777 - lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
778 - MTK_PHY_RXADC_CTRL_RG9,
779 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
780 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
781 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
782 - MTK_PHY_DA_RX_PSBN_LP_MASK,
783 - lower_idx << 12 | lower_idx << 8 |
784 - lower_idx << 4 | lower_idx);
785 - ret = lower_ret;
786 - } else if (upper_idx == TXRESERVE_MAX) {
787 - upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
788 - MTK_PHY_RXADC_CTRL_RG9,
789 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
790 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
791 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
792 - MTK_PHY_DA_RX_PSBN_LP_MASK,
793 - upper_idx << 12 | upper_idx << 8 |
794 - upper_idx << 4 | upper_idx);
795 - ret = upper_ret;
796 - }
797 - if (ret < 0)
798 - goto restore;
799 -
800 - /* We calibrate TX-VCM in different logic. Check upper index and then
801 - * lower index. If this calibration is valid, apply lower index's
802 - * result.
803 - */
804 - ret = upper_ret - lower_ret;
805 - if (ret == 1) {
806 - ret = 0;
807 - /* Make sure we use upper_idx in our calibration system */
808 - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
809 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
810 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
811 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
812 - MTK_PHY_DA_RX_PSBN_LP_MASK,
813 - upper_idx << 12 | upper_idx << 8 |
814 - upper_idx << 4 | upper_idx);
815 - phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
816 - } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
817 - lower_ret == 1) {
818 - ret = 0;
819 - cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
820 - MTK_PHY_DA_RX_PSBN_TBT_MASK |
821 - MTK_PHY_DA_RX_PSBN_HBT_MASK |
822 - MTK_PHY_DA_RX_PSBN_GBE_MASK |
823 - MTK_PHY_DA_RX_PSBN_LP_MASK,
824 - lower_idx << 12 | lower_idx << 8 |
825 - lower_idx << 4 | lower_idx);
826 - phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
827 - lower_idx);
828 - } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
829 - lower_ret == 0) {
830 - ret = 0;
831 - phydev_warn(phydev,
832 - "TX-VCM SW cal result at high margin 0x%x\n",
833 - upper_idx);
834 - } else {
835 - ret = -EINVAL;
836 - }
837 -
838 -restore:
839 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
840 - MTK_PHY_RG_ANA_CALEN);
841 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
842 - MTK_PHY_RG_TXVOS_CALEN);
843 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
844 - MTK_PHY_RG_ZCALEN_A);
845 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
846 - MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
847 - MTK_PHY_RG_ZCALEN_D);
848 -
849 - return ret;
850 -}
851 -
852 -static void mt798x_phy_common_finetune(struct phy_device *phydev)
853 -{
854 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
855 - /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
856 - __phy_write(phydev, 0x11, 0xc71);
857 - __phy_write(phydev, 0x12, 0xc);
858 - __phy_write(phydev, 0x10, 0x8fae);
859 -
860 - /* EnabRandUpdTrig = 1 */
861 - __phy_write(phydev, 0x11, 0x2f00);
862 - __phy_write(phydev, 0x12, 0xe);
863 - __phy_write(phydev, 0x10, 0x8fb0);
864 -
865 - /* NormMseLoThresh = 85 */
866 - __phy_write(phydev, 0x11, 0x55a0);
867 - __phy_write(phydev, 0x12, 0x0);
868 - __phy_write(phydev, 0x10, 0x83aa);
869 -
870 - /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
871 - __phy_write(phydev, 0x11, 0x240);
872 - __phy_write(phydev, 0x12, 0x0);
873 - __phy_write(phydev, 0x10, 0x9680);
874 -
875 - /* TrFreeze = 0 (mt7988 default) */
876 - __phy_write(phydev, 0x11, 0x0);
877 - __phy_write(phydev, 0x12, 0x0);
878 - __phy_write(phydev, 0x10, 0x9686);
879 -
880 - /* SSTrKp100 = 5 */
881 - /* SSTrKf100 = 6 */
882 - /* SSTrKp1000Mas = 5 */
883 - /* SSTrKf1000Mas = 6 */
884 - /* SSTrKp1000Slv = 5 */
885 - /* SSTrKf1000Slv = 6 */
886 - __phy_write(phydev, 0x11, 0xbaef);
887 - __phy_write(phydev, 0x12, 0x2e);
888 - __phy_write(phydev, 0x10, 0x968c);
889 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
890 -}
891 -
892 -static void mt7981_phy_finetune(struct phy_device *phydev)
893 -{
894 - u16 val[8] = { 0x01ce, 0x01c1,
895 - 0x020f, 0x0202,
896 - 0x03d0, 0x03c0,
897 - 0x0013, 0x0005 };
898 - int i, k;
899 -
900 - /* 100M eye finetune:
901 - * Keep middle level of TX MLT3 shapper as default.
902 - * Only change TX MLT3 overshoot level here.
903 - */
904 - for (k = 0, i = 1; i < 12; i++) {
905 - if (i % 3 == 0)
906 - continue;
907 - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
908 - }
909 -
910 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
911 - /* ResetSyncOffset = 6 */
912 - __phy_write(phydev, 0x11, 0x600);
913 - __phy_write(phydev, 0x12, 0x0);
914 - __phy_write(phydev, 0x10, 0x8fc0);
915 -
916 - /* VgaDecRate = 1 */
917 - __phy_write(phydev, 0x11, 0x4c2a);
918 - __phy_write(phydev, 0x12, 0x3e);
919 - __phy_write(phydev, 0x10, 0x8fa4);
920 -
921 - /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
922 - * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
923 - */
924 - __phy_write(phydev, 0x11, 0xd10a);
925 - __phy_write(phydev, 0x12, 0x34);
926 - __phy_write(phydev, 0x10, 0x8f82);
927 -
928 - /* VcoSlicerThreshBitsHigh */
929 - __phy_write(phydev, 0x11, 0x5555);
930 - __phy_write(phydev, 0x12, 0x55);
931 - __phy_write(phydev, 0x10, 0x8ec0);
932 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
933 -
934 - /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
935 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
936 - MTK_PHY_TR_OPEN_LOOP_EN_MASK |
937 - MTK_PHY_LPF_X_AVERAGE_MASK,
938 - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
939 -
940 - /* rg_tr_lpf_cnt_val = 512 */
941 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
942 -
943 - /* IIR2 related */
944 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
945 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
946 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
947 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
948 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
949 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
950 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
951 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
952 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
953 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
954 -
955 - /* FFE peaking */
956 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
957 - MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
958 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
959 - MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
960 -
961 - /* Disable LDO pump */
962 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
963 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
964 - /* Adjust LDO output voltage */
965 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
966 -}
967 -
968 -static void mt7988_phy_finetune(struct phy_device *phydev)
969 -{
970 - u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
971 - 0x020d, 0x0206, 0x0384, 0x03d0,
972 - 0x03c6, 0x030a, 0x0011, 0x0005 };
973 - int i;
974 -
975 - /* Set default MLT3 shaper first */
976 - for (i = 0; i < 12; i++)
977 - phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
978 -
979 - /* TCT finetune */
980 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
981 -
982 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
983 - /* ResetSyncOffset = 5 */
984 - __phy_write(phydev, 0x11, 0x500);
985 - __phy_write(phydev, 0x12, 0x0);
986 - __phy_write(phydev, 0x10, 0x8fc0);
987 -
988 - /* VgaDecRate is 1 at default on mt7988 */
989 -
990 - /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
991 - * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
992 - */
993 - __phy_write(phydev, 0x11, 0xb90a);
994 - __phy_write(phydev, 0x12, 0x6f);
995 - __phy_write(phydev, 0x10, 0x8f82);
996 -
997 - /* RemAckCntLimitCtrl = 1 */
998 - __phy_write(phydev, 0x11, 0xfbba);
999 - __phy_write(phydev, 0x12, 0xc3);
1000 - __phy_write(phydev, 0x10, 0x87f8);
1001 -
1002 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1003 -
1004 - /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
1005 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
1006 - MTK_PHY_TR_OPEN_LOOP_EN_MASK |
1007 - MTK_PHY_LPF_X_AVERAGE_MASK,
1008 - BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
1009 -
1010 - /* rg_tr_lpf_cnt_val = 1023 */
1011 - phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
1012 -}
1013 -
1014 -static void mt798x_phy_eee(struct phy_device *phydev)
1015 -{
1016 - phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1017 - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
1018 - MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
1019 - MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
1020 - FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
1021 - FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
1022 -
1023 - phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1024 - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
1025 - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1026 - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1027 - 0xff));
1028 -
1029 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1030 - MTK_PHY_RG_TESTMUX_ADC_CTRL,
1031 - MTK_PHY_RG_TXEN_DIG_MASK);
1032 -
1033 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1034 - MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
1035 -
1036 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1037 - MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
1038 -
1039 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
1040 - MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
1041 - MTK_PHY_LPI_SLV_SEND_TX_EN,
1042 - FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
1043 -
1044 - /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
1045 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
1046 - MTK_PHY_LPI_TXPCS_LOC_RCV);
1047 -
1048 - /* This also fixes some IoT issues, such as CH340 */
1049 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
1050 - MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
1051 - FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
1052 - FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
1053 -
1054 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
1055 - MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
1056 - FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
1057 - 0x33) |
1058 - MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
1059 - MTK_PHY_LPI_VCO_EEE_STG0_EN);
1060 -
1061 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
1062 - MTK_PHY_EEE_WAKE_MAS_INT_DC |
1063 - MTK_PHY_EEE_WAKE_SLV_INT_DC);
1064 -
1065 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
1066 - MTK_PHY_SMI_DETCNT_MAX_MASK,
1067 - FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
1068 - MTK_PHY_SMI_DET_MAX_EN);
1069 -
1070 - phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
1071 - MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
1072 - MTK_PHY_TREC_UPDATE_ENAB_CLR |
1073 - MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
1074 - MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
1075 -
1076 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
1077 - /* Regsigdet_sel_1000 = 0 */
1078 - __phy_write(phydev, 0x11, 0xb);
1079 - __phy_write(phydev, 0x12, 0x0);
1080 - __phy_write(phydev, 0x10, 0x9690);
1081 -
1082 - /* REG_EEE_st2TrKf1000 = 2 */
1083 - __phy_write(phydev, 0x11, 0x114f);
1084 - __phy_write(phydev, 0x12, 0x2);
1085 - __phy_write(phydev, 0x10, 0x969a);
1086 -
1087 - /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
1088 - __phy_write(phydev, 0x11, 0x3028);
1089 - __phy_write(phydev, 0x12, 0x0);
1090 - __phy_write(phydev, 0x10, 0x969e);
1091 -
1092 - /* RegEEE_slv_wake_int_timer_tar = 8 */
1093 - __phy_write(phydev, 0x11, 0x5010);
1094 - __phy_write(phydev, 0x12, 0x0);
1095 - __phy_write(phydev, 0x10, 0x96a0);
1096 -
1097 - /* RegEEE_trfreeze_timer2 = 586 */
1098 - __phy_write(phydev, 0x11, 0x24a);
1099 - __phy_write(phydev, 0x12, 0x0);
1100 - __phy_write(phydev, 0x10, 0x96a8);
1101 -
1102 - /* RegEEE100Stg1_tar = 16 */
1103 - __phy_write(phydev, 0x11, 0x3210);
1104 - __phy_write(phydev, 0x12, 0x0);
1105 - __phy_write(phydev, 0x10, 0x96b8);
1106 -
1107 - /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
1108 - __phy_write(phydev, 0x11, 0x1463);
1109 - __phy_write(phydev, 0x12, 0x0);
1110 - __phy_write(phydev, 0x10, 0x96ca);
1111 -
1112 - /* DfeTailEnableVgaThresh1000 = 27 */
1113 - __phy_write(phydev, 0x11, 0x36);
1114 - __phy_write(phydev, 0x12, 0x0);
1115 - __phy_write(phydev, 0x10, 0x8f80);
1116 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1117 -
1118 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
1119 - __phy_modify(phydev, MTK_PHY_LPI_REG_14,
1120 - MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
1121 - FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
1122 -
1123 - __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
1124 - FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
1125 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1126 -
1127 - phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1128 - MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
1129 - MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1130 - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
1131 - 0xff));
1132 -}
1133 -
1134 -static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
1135 - u8 start_pair, u8 end_pair)
1136 -{
1137 - u8 pair_n;
1138 - int ret;
1139 -
1140 - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1141 - /* TX_OFFSET & TX_AMP have no SW calibration. */
1142 - switch (cal_item) {
1143 - case TX_VCM:
1144 - ret = tx_vcm_cal_sw(phydev, pair_n);
1145 - break;
1146 - default:
1147 - return -EINVAL;
1148 - }
1149 - if (ret)
1150 - return ret;
1151 - }
1152 - return 0;
1153 -}
1154 -
1155 -static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
1156 - u8 start_pair, u8 end_pair, u32 *buf)
1157 -{
1158 - u8 pair_n;
1159 - int ret;
1160 -
1161 - for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
1162 - /* TX_VCM has no efuse calibration. */
1163 - switch (cal_item) {
1164 - case REXT:
1165 - ret = rext_cal_efuse(phydev, buf);
1166 - break;
1167 - case TX_OFFSET:
1168 - ret = tx_offset_cal_efuse(phydev, buf);
1169 - break;
1170 - case TX_AMP:
1171 - ret = tx_amp_cal_efuse(phydev, buf);
1172 - break;
1173 - case TX_R50:
1174 - ret = tx_r50_cal_efuse(phydev, buf, pair_n);
1175 - break;
1176 - default:
1177 - return -EINVAL;
1178 - }
1179 - if (ret)
1180 - return ret;
1181 - }
1182 -
1183 - return 0;
1184 -}
1185 -
1186 -static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
1187 - enum CAL_MODE cal_mode, u8 start_pair,
1188 - u8 end_pair, u32 *buf)
1189 -{
1190 - int ret;
1191 -
1192 - switch (cal_mode) {
1193 - case EFUSE_M:
1194 - ret = cal_efuse(phydev, cal_item, start_pair,
1195 - end_pair, buf);
1196 - break;
1197 - case SW_M:
1198 - ret = cal_sw(phydev, cal_item, start_pair, end_pair);
1199 - break;
1200 - default:
1201 - return -EINVAL;
1202 - }
1203 -
1204 - if (ret) {
1205 - phydev_err(phydev, "cal %d failed\n", cal_item);
1206 - return -EIO;
1207 - }
1208 -
1209 - return 0;
1210 -}
1211 -
1212 -static int mt798x_phy_calibration(struct phy_device *phydev)
1213 -{
1214 - struct nvmem_cell *cell;
1215 - int ret = 0;
1216 - size_t len;
1217 - u32 *buf;
1218 -
1219 - cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
1220 - if (IS_ERR(cell)) {
1221 - if (PTR_ERR(cell) == -EPROBE_DEFER)
1222 - return PTR_ERR(cell);
1223 - return 0;
1224 - }
1225 -
1226 - buf = (u32 *)nvmem_cell_read(cell, &len);
1227 - if (IS_ERR(buf))
1228 - return PTR_ERR(buf);
1229 - nvmem_cell_put(cell);
1230 -
1231 - if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
1232 - phydev_err(phydev, "invalid efuse data\n");
1233 - ret = -EINVAL;
1234 - goto out;
1235 - }
1236 -
1237 - ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1238 - if (ret)
1239 - goto out;
1240 - ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1241 - if (ret)
1242 - goto out;
1243 - ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
1244 - if (ret)
1245 - goto out;
1246 - ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
1247 - if (ret)
1248 - goto out;
1249 - ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
1250 - if (ret)
1251 - goto out;
1252 -
1253 -out:
1254 - kfree(buf);
1255 - return ret;
1256 -}
1257 -
1258 -static int mt798x_phy_config_init(struct phy_device *phydev)
1259 -{
1260 - switch (phydev->drv->phy_id) {
1261 - case MTK_GPHY_ID_MT7981:
1262 - mt7981_phy_finetune(phydev);
1263 - break;
1264 - case MTK_GPHY_ID_MT7988:
1265 - mt7988_phy_finetune(phydev);
1266 - break;
1267 - }
1268 -
1269 - mt798x_phy_common_finetune(phydev);
1270 - mt798x_phy_eee(phydev);
1271 -
1272 - return mt798x_phy_calibration(phydev);
1273 -}
1274 -
1275 -static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
1276 - bool on)
1277 -{
1278 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
1279 - struct mtk_socphy_priv *priv = phydev->priv;
1280 - bool changed;
1281 -
1282 - if (on)
1283 - changed = !test_and_set_bit(bit_on, &priv->led_state);
1284 - else
1285 - changed = !!test_and_clear_bit(bit_on, &priv->led_state);
1286 -
1287 - changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
1288 - (index ? 16 : 0), &priv->led_state);
1289 - if (changed)
1290 - return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1291 - MTK_PHY_LED1_ON_CTRL :
1292 - MTK_PHY_LED0_ON_CTRL,
1293 - MTK_PHY_LED_ON_MASK,
1294 - on ? MTK_PHY_LED_ON_FORCE_ON : 0);
1295 - else
1296 - return 0;
1297 -}
1298 -
1299 -static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
1300 - bool blinking)
1301 -{
1302 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
1303 - (index ? 16 : 0);
1304 - struct mtk_socphy_priv *priv = phydev->priv;
1305 - bool changed;
1306 -
1307 - if (blinking)
1308 - changed = !test_and_set_bit(bit_blink, &priv->led_state);
1309 - else
1310 - changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
1311 -
1312 - changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
1313 - (index ? 16 : 0), &priv->led_state);
1314 - if (changed)
1315 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1316 - MTK_PHY_LED1_BLINK_CTRL :
1317 - MTK_PHY_LED0_BLINK_CTRL,
1318 - blinking ?
1319 - MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
1320 - else
1321 - return 0;
1322 -}
1323 -
1324 -static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
1325 - unsigned long *delay_on,
1326 - unsigned long *delay_off)
1327 -{
1328 - bool blinking = false;
1329 - int err = 0;
1330 -
1331 - if (index > 1)
1332 - return -EINVAL;
1333 -
1334 - if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
1335 - blinking = true;
1336 - *delay_on = 50;
1337 - *delay_off = 50;
1338 - }
1339 -
1340 - err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
1341 - if (err)
1342 - return err;
1343 -
1344 - return mt798x_phy_hw_led_on_set(phydev, index, false);
1345 -}
1346 -
1347 -static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
1348 - u8 index, enum led_brightness value)
1349 -{
1350 - int err;
1351 -
1352 - err = mt798x_phy_hw_led_blink_set(phydev, index, false);
1353 - if (err)
1354 - return err;
1355 -
1356 - return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
1357 -}
1358 -
1359 -static const unsigned long supported_triggers =
1360 - BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
1361 - BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
1362 - BIT(TRIGGER_NETDEV_LINK) |
1363 - BIT(TRIGGER_NETDEV_LINK_10) |
1364 - BIT(TRIGGER_NETDEV_LINK_100) |
1365 - BIT(TRIGGER_NETDEV_LINK_1000) |
1366 - BIT(TRIGGER_NETDEV_RX) |
1367 - BIT(TRIGGER_NETDEV_TX);
1368 -
1369 -static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
1370 - unsigned long rules)
1371 -{
1372 - if (index > 1)
1373 - return -EINVAL;
1374 -
1375 - /* All combinations of the supported triggers are allowed */
1376 - if (rules & ~supported_triggers)
1377 - return -EOPNOTSUPP;
1378 -
1379 - return 0;
1380 -};
1381 -
1382 -static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
1383 - unsigned long *rules)
1384 -{
1385 - unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
1386 - (index ? 16 : 0);
1387 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
1388 - unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
1389 - struct mtk_socphy_priv *priv = phydev->priv;
1390 - int on, blink;
1391 -
1392 - if (index > 1)
1393 - return -EINVAL;
1394 -
1395 - on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1396 - index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
1397 -
1398 - if (on < 0)
1399 - return -EIO;
1400 -
1401 - blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1402 - index ? MTK_PHY_LED1_BLINK_CTRL :
1403 - MTK_PHY_LED0_BLINK_CTRL);
1404 - if (blink < 0)
1405 - return -EIO;
1406 -
1407 - if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
1408 - MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
1409 - (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
1410 - set_bit(bit_netdev, &priv->led_state);
1411 - else
1412 - clear_bit(bit_netdev, &priv->led_state);
1413 -
1414 - if (on & MTK_PHY_LED_ON_FORCE_ON)
1415 - set_bit(bit_on, &priv->led_state);
1416 - else
1417 - clear_bit(bit_on, &priv->led_state);
1418 -
1419 - if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
1420 - set_bit(bit_blink, &priv->led_state);
1421 - else
1422 - clear_bit(bit_blink, &priv->led_state);
1423 -
1424 - if (!rules)
1425 - return 0;
1426 -
1427 - if (on & MTK_PHY_LED_ON_LINK)
1428 - *rules |= BIT(TRIGGER_NETDEV_LINK);
1429 -
1430 - if (on & MTK_PHY_LED_ON_LINK10)
1431 - *rules |= BIT(TRIGGER_NETDEV_LINK_10);
1432 -
1433 - if (on & MTK_PHY_LED_ON_LINK100)
1434 - *rules |= BIT(TRIGGER_NETDEV_LINK_100);
1435 -
1436 - if (on & MTK_PHY_LED_ON_LINK1000)
1437 - *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
1438 -
1439 - if (on & MTK_PHY_LED_ON_FDX)
1440 - *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
1441 -
1442 - if (on & MTK_PHY_LED_ON_HDX)
1443 - *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
1444 -
1445 - if (blink & MTK_PHY_LED_BLINK_RX)
1446 - *rules |= BIT(TRIGGER_NETDEV_RX);
1447 -
1448 - if (blink & MTK_PHY_LED_BLINK_TX)
1449 - *rules |= BIT(TRIGGER_NETDEV_TX);
1450 -
1451 - return 0;
1452 -};
1453 -
1454 -static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
1455 - unsigned long rules)
1456 -{
1457 - unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
1458 - struct mtk_socphy_priv *priv = phydev->priv;
1459 - u16 on = 0, blink = 0;
1460 - int ret;
1461 -
1462 - if (index > 1)
1463 - return -EINVAL;
1464 -
1465 - if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
1466 - on |= MTK_PHY_LED_ON_FDX;
1467 -
1468 - if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
1469 - on |= MTK_PHY_LED_ON_HDX;
1470 -
1471 - if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
1472 - on |= MTK_PHY_LED_ON_LINK10;
1473 -
1474 - if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
1475 - on |= MTK_PHY_LED_ON_LINK100;
1476 -
1477 - if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
1478 - on |= MTK_PHY_LED_ON_LINK1000;
1479 -
1480 - if (rules & BIT(TRIGGER_NETDEV_RX)) {
1481 - blink |= (on & MTK_PHY_LED_ON_LINK) ?
1482 - (((on & MTK_PHY_LED_ON_LINK10) ?
1483 - MTK_PHY_LED_BLINK_10RX : 0) |
1484 - ((on & MTK_PHY_LED_ON_LINK100) ?
1485 - MTK_PHY_LED_BLINK_100RX : 0) |
1486 - ((on & MTK_PHY_LED_ON_LINK1000) ?
1487 - MTK_PHY_LED_BLINK_1000RX : 0)) :
1488 - MTK_PHY_LED_BLINK_RX;
1489 - }
1490 -
1491 - if (rules & BIT(TRIGGER_NETDEV_TX)) {
1492 - blink |= (on & MTK_PHY_LED_ON_LINK) ?
1493 - (((on & MTK_PHY_LED_ON_LINK10) ?
1494 - MTK_PHY_LED_BLINK_10TX : 0) |
1495 - ((on & MTK_PHY_LED_ON_LINK100) ?
1496 - MTK_PHY_LED_BLINK_100TX : 0) |
1497 - ((on & MTK_PHY_LED_ON_LINK1000) ?
1498 - MTK_PHY_LED_BLINK_1000TX : 0)) :
1499 - MTK_PHY_LED_BLINK_TX;
1500 - }
1501 -
1502 - if (blink || on)
1503 - set_bit(bit_netdev, &priv->led_state);
1504 - else
1505 - clear_bit(bit_netdev, &priv->led_state);
1506 -
1507 - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1508 - MTK_PHY_LED1_ON_CTRL :
1509 - MTK_PHY_LED0_ON_CTRL,
1510 - MTK_PHY_LED_ON_FDX |
1511 - MTK_PHY_LED_ON_HDX |
1512 - MTK_PHY_LED_ON_LINK,
1513 - on);
1514 -
1515 - if (ret)
1516 - return ret;
1517 -
1518 - return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
1519 - MTK_PHY_LED1_BLINK_CTRL :
1520 - MTK_PHY_LED0_BLINK_CTRL, blink);
1521 -};
1522 -
1523 -static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
1524 -{
1525 - struct mtk_socphy_shared *priv = phydev->shared->priv;
1526 - u32 polarities;
1527 -
1528 - if (led_num == 0)
1529 - polarities = ~(priv->boottrap);
1530 - else
1531 - polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
1532 -
1533 - if (polarities & BIT(phydev->mdio.addr))
1534 - return true;
1535 -
1536 - return false;
1537 -}
1538 -
1539 -static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
1540 -{
1541 - struct pinctrl *pinctrl;
1542 - int index;
1543 -
1544 - /* Setup LED polarity according to bootstrap use of LED pins */
1545 - for (index = 0; index < 2; ++index)
1546 - phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
1547 - MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
1548 - MTK_PHY_LED_ON_POLARITY,
1549 - mt7988_phy_led_get_polarity(phydev, index) ?
1550 - MTK_PHY_LED_ON_POLARITY : 0);
1551 -
1552 - /* Only now setup pinctrl to avoid bogus blinking */
1553 - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
1554 - if (IS_ERR(pinctrl))
1555 - dev_err(&phydev->mdio.bus->dev,
1556 - "Failed to setup PHY LED pinctrl\n");
1557 -
1558 - return 0;
1559 -}
1560 -
1561 -static int mt7988_phy_probe_shared(struct phy_device *phydev)
1562 -{
1563 - struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
1564 - struct mtk_socphy_shared *shared = phydev->shared->priv;
1565 - struct regmap *regmap;
1566 - u32 reg;
1567 - int ret;
1568 -
1569 - /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
1570 - * LED_C and LED_D respectively. At the same time those pins are used to
1571 - * bootstrap configuration of the reference clock source (LED_A),
1572 - * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
1573 - * In practice this is done using a LED and a resistor pulling the pin
1574 - * either to GND or to VIO.
1575 - * The detected value at boot time is accessible at run-time using the
1576 - * TPBANK0 register located in the gpio base of the pinctrl, in order
1577 - * to read it here it needs to be referenced by a phandle called
1578 - * 'mediatek,pio' in the MDIO bus hosting the PHY.
1579 - * The 4 bits in TPBANK0 are kept as package shared data and are used to
1580 - * set LED polarity for each of the LED0.
1581 - */
1582 - regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
1583 - if (IS_ERR(regmap))
1584 - return PTR_ERR(regmap);
1585 -
1586 - ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
1587 - if (ret)
1588 - return ret;
1589 -
1590 - shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
1591 -
1592 - return 0;
1593 -}
1594 -
1595 -static void mt798x_phy_leds_state_init(struct phy_device *phydev)
1596 -{
1597 - int i;
1598 -
1599 - for (i = 0; i < 2; ++i)
1600 - mt798x_phy_led_hw_control_get(phydev, i, NULL);
1601 -}
1602 -
1603 -static int mt7988_phy_probe(struct phy_device *phydev)
1604 -{
1605 - struct mtk_socphy_shared *shared;
1606 - struct mtk_socphy_priv *priv;
1607 - int err;
1608 -
1609 - if (phydev->mdio.addr > 3)
1610 - return -EINVAL;
1611 -
1612 - err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
1613 - sizeof(struct mtk_socphy_shared));
1614 - if (err)
1615 - return err;
1616 -
1617 - if (phy_package_probe_once(phydev)) {
1618 - err = mt7988_phy_probe_shared(phydev);
1619 - if (err)
1620 - return err;
1621 - }
1622 -
1623 - shared = phydev->shared->priv;
1624 - priv = &shared->priv[phydev->mdio.addr];
1625 -
1626 - phydev->priv = priv;
1627 -
1628 - mt798x_phy_leds_state_init(phydev);
1629 -
1630 - err = mt7988_phy_fix_leds_polarities(phydev);
1631 - if (err)
1632 - return err;
1633 -
1634 - /* Disable TX power saving at probing to:
1635 - * 1. Meet common mode compliance test criteria
1636 - * 2. Make sure that TX-VCM calibration works fine
1637 - */
1638 - phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
1639 - MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
1640 -
1641 - return mt798x_phy_calibration(phydev);
1642 -}
1643 -
1644 -static int mt7981_phy_probe(struct phy_device *phydev)
1645 -{
1646 - struct mtk_socphy_priv *priv;
1647 -
1648 - priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
1649 - GFP_KERNEL);
1650 - if (!priv)
1651 - return -ENOMEM;
1652 -
1653 - phydev->priv = priv;
1654 -
1655 - mt798x_phy_leds_state_init(phydev);
1656 -
1657 - return mt798x_phy_calibration(phydev);
1658 -}
1659 -
1660 -static struct phy_driver mtk_socphy_driver[] = {
1661 - {
1662 - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
1663 - .name = "MediaTek MT7981 PHY",
1664 - .config_init = mt798x_phy_config_init,
1665 - .config_intr = genphy_no_config_intr,
1666 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1667 - .probe = mt7981_phy_probe,
1668 - .suspend = genphy_suspend,
1669 - .resume = genphy_resume,
1670 - .read_page = mtk_socphy_read_page,
1671 - .write_page = mtk_socphy_write_page,
1672 - .led_blink_set = mt798x_phy_led_blink_set,
1673 - .led_brightness_set = mt798x_phy_led_brightness_set,
1674 - .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1675 - .led_hw_control_set = mt798x_phy_led_hw_control_set,
1676 - .led_hw_control_get = mt798x_phy_led_hw_control_get,
1677 - },
1678 - {
1679 - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
1680 - .name = "MediaTek MT7988 PHY",
1681 - .config_init = mt798x_phy_config_init,
1682 - .config_intr = genphy_no_config_intr,
1683 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1684 - .probe = mt7988_phy_probe,
1685 - .suspend = genphy_suspend,
1686 - .resume = genphy_resume,
1687 - .read_page = mtk_socphy_read_page,
1688 - .write_page = mtk_socphy_write_page,
1689 - .led_blink_set = mt798x_phy_led_blink_set,
1690 - .led_brightness_set = mt798x_phy_led_brightness_set,
1691 - .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
1692 - .led_hw_control_set = mt798x_phy_led_hw_control_set,
1693 - .led_hw_control_get = mt798x_phy_led_hw_control_get,
1694 - },
1695 -};
1696 -
1697 -module_phy_driver(mtk_socphy_driver);
1698 -
1699 -static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
1700 - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
1701 - { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
1702 - { }
1703 -};
1704 -
1705 -MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
1706 -MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1707 -MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
1708 -MODULE_LICENSE("GPL");
1709 -
1710 -MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
1711 --- a/drivers/net/phy/mediatek-ge.c
1712 +++ /dev/null
1713 @@ -1,114 +0,0 @@
1714 -// SPDX-License-Identifier: GPL-2.0+
1715 -#include <linux/bitfield.h>
1716 -#include <linux/module.h>
1717 -#include <linux/phy.h>
1718 -
1719 -#define MTK_EXT_PAGE_ACCESS 0x1f
1720 -#define MTK_PHY_PAGE_STANDARD 0x0000
1721 -#define MTK_PHY_PAGE_EXTENDED 0x0001
1722 -#define MTK_PHY_PAGE_EXTENDED_2 0x0002
1723 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003
1724 -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
1725 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
1726 -
1727 -static int mtk_gephy_read_page(struct phy_device *phydev)
1728 -{
1729 - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
1730 -}
1731 -
1732 -static int mtk_gephy_write_page(struct phy_device *phydev, int page)
1733 -{
1734 - return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
1735 -}
1736 -
1737 -static void mtk_gephy_config_init(struct phy_device *phydev)
1738 -{
1739 - /* Disable EEE */
1740 - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
1741 -
1742 - /* Enable HW auto downshift */
1743 - phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
1744 -
1745 - /* Increase SlvDPSready time */
1746 - phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
1747 - __phy_write(phydev, 0x10, 0xafae);
1748 - __phy_write(phydev, 0x12, 0x2f);
1749 - __phy_write(phydev, 0x10, 0x8fae);
1750 - phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
1751 -
1752 - /* Adjust 100_mse_threshold */
1753 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
1754 -
1755 - /* Disable mcc */
1756 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
1757 -}
1758 -
1759 -static int mt7530_phy_config_init(struct phy_device *phydev)
1760 -{
1761 - mtk_gephy_config_init(phydev);
1762 -
1763 - /* Increase post_update_timer */
1764 - phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
1765 -
1766 - return 0;
1767 -}
1768 -
1769 -static int mt7531_phy_config_init(struct phy_device *phydev)
1770 -{
1771 - mtk_gephy_config_init(phydev);
1772 -
1773 - /* PHY link down power saving enable */
1774 - phy_set_bits(phydev, 0x17, BIT(4));
1775 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
1776 -
1777 - /* Set TX Pair delay selection */
1778 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
1779 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
1780 -
1781 - return 0;
1782 -}
1783 -
1784 -static struct phy_driver mtk_gephy_driver[] = {
1785 - {
1786 - PHY_ID_MATCH_EXACT(0x03a29412),
1787 - .name = "MediaTek MT7530 PHY",
1788 - .config_init = mt7530_phy_config_init,
1789 - /* Interrupts are handled by the switch, not the PHY
1790 - * itself.
1791 - */
1792 - .config_intr = genphy_no_config_intr,
1793 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1794 - .suspend = genphy_suspend,
1795 - .resume = genphy_resume,
1796 - .read_page = mtk_gephy_read_page,
1797 - .write_page = mtk_gephy_write_page,
1798 - },
1799 - {
1800 - PHY_ID_MATCH_EXACT(0x03a29441),
1801 - .name = "MediaTek MT7531 PHY",
1802 - .config_init = mt7531_phy_config_init,
1803 - /* Interrupts are handled by the switch, not the PHY
1804 - * itself.
1805 - */
1806 - .config_intr = genphy_no_config_intr,
1807 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1808 - .suspend = genphy_suspend,
1809 - .resume = genphy_resume,
1810 - .read_page = mtk_gephy_read_page,
1811 - .write_page = mtk_gephy_write_page,
1812 - },
1813 -};
1814 -
1815 -module_phy_driver(mtk_gephy_driver);
1816 -
1817 -static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
1818 - { PHY_ID_MATCH_EXACT(0x03a29441) },
1819 - { PHY_ID_MATCH_EXACT(0x03a29412) },
1820 - { }
1821 -};
1822 -
1823 -MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
1824 -MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
1825 -MODULE_LICENSE("GPL");
1826 -
1827 -MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
1828 --- /dev/null
1829 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
1830 @@ -0,0 +1,1610 @@
1831 +// SPDX-License-Identifier: GPL-2.0+
1832 +#include <linux/bitfield.h>
1833 +#include <linux/bitmap.h>
1834 +#include <linux/mfd/syscon.h>
1835 +#include <linux/module.h>
1836 +#include <linux/nvmem-consumer.h>
1837 +#include <linux/pinctrl/consumer.h>
1838 +#include <linux/phy.h>
1839 +#include <linux/regmap.h>
1840 +
1841 +#define MTK_GPHY_ID_MT7981 0x03a29461
1842 +#define MTK_GPHY_ID_MT7988 0x03a29481
1843 +
1844 +#define MTK_EXT_PAGE_ACCESS 0x1f
1845 +#define MTK_PHY_PAGE_STANDARD 0x0000
1846 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
1847 +
1848 +#define MTK_PHY_LPI_REG_14 0x14
1849 +#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
1850 +
1851 +#define MTK_PHY_LPI_REG_1c 0x1c
1852 +#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
1853 +
1854 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
1855 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
1856 +
1857 +#define ANALOG_INTERNAL_OPERATION_MAX_US 20
1858 +#define TXRESERVE_MIN 0
1859 +#define TXRESERVE_MAX 7
1860 +
1861 +#define MTK_PHY_ANARG_RG 0x10
1862 +#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
1863 +
1864 +/* Registers on MDIO_MMD_VEND1 */
1865 +#define MTK_PHY_TXVLD_DA_RG 0x12
1866 +#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
1867 +#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
1868 +
1869 +#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
1870 +#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
1871 +#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
1872 +
1873 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
1874 +#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
1875 +#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
1876 +
1877 +#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
1878 +#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
1879 +#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
1880 +
1881 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
1882 +#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
1883 +#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
1884 +
1885 +#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
1886 +#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
1887 +#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
1888 +
1889 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
1890 +#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
1891 +#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
1892 +
1893 +#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
1894 +#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
1895 +#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
1896 +
1897 +#define MTK_PHY_RXADC_CTRL_RG7 0xc6
1898 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
1899 +
1900 +#define MTK_PHY_RXADC_CTRL_RG9 0xc8
1901 +#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
1902 +#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
1903 +#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
1904 +#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
1905 +
1906 +#define MTK_PHY_LDO_OUTPUT_V 0xd7
1907 +
1908 +#define MTK_PHY_RG_ANA_CAL_RG0 0xdb
1909 +#define MTK_PHY_RG_CAL_CKINV BIT(12)
1910 +#define MTK_PHY_RG_ANA_CALEN BIT(8)
1911 +#define MTK_PHY_RG_ZCALEN_A BIT(0)
1912 +
1913 +#define MTK_PHY_RG_ANA_CAL_RG1 0xdc
1914 +#define MTK_PHY_RG_ZCALEN_B BIT(12)
1915 +#define MTK_PHY_RG_ZCALEN_C BIT(8)
1916 +#define MTK_PHY_RG_ZCALEN_D BIT(4)
1917 +#define MTK_PHY_RG_TXVOS_CALEN BIT(0)
1918 +
1919 +#define MTK_PHY_RG_ANA_CAL_RG5 0xe0
1920 +#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
1921 +
1922 +#define MTK_PHY_RG_TX_FILTER 0xfe
1923 +
1924 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
1925 +#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
1926 +#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
1927 +
1928 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
1929 +#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
1930 +
1931 +#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
1932 +#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
1933 +
1934 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
1935 +#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
1936 +#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
1937 +
1938 +#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
1939 +#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
1940 +#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
1941 +
1942 +#define MTK_PHY_RG_AD_CAL_COMP 0x17a
1943 +#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8)
1944 +
1945 +#define MTK_PHY_RG_AD_CAL_CLK 0x17b
1946 +#define MTK_PHY_DA_CAL_CLK BIT(0)
1947 +
1948 +#define MTK_PHY_RG_AD_CALIN 0x17c
1949 +#define MTK_PHY_DA_CALIN_FLAG BIT(0)
1950 +
1951 +#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
1952 +#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
1953 +
1954 +#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
1955 +#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
1956 +
1957 +#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
1958 +#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
1959 +
1960 +#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
1961 +#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
1962 +
1963 +#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
1964 +#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
1965 +
1966 +#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
1967 +#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
1968 +
1969 +#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
1970 +#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
1971 +
1972 +#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
1973 +#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
1974 +
1975 +#define MTK_PHY_RG_DEV1E_REG19b 0x19b
1976 +#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
1977 +
1978 +#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
1979 +#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
1980 +#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
1981 +#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
1982 +#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
1983 +#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
1984 +#define MTK_PHY_RG_LP_IIR2_K4_L 0x230
1985 +#define MTK_PHY_RG_LP_IIR2_K4_U 0x231
1986 +#define MTK_PHY_RG_LP_IIR2_K5_L 0x232
1987 +#define MTK_PHY_RG_LP_IIR2_K5_U 0x233
1988 +
1989 +#define MTK_PHY_RG_DEV1E_REG234 0x234
1990 +#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
1991 +#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
1992 +#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
1993 +
1994 +#define MTK_PHY_RG_LPF_CNT_VAL 0x235
1995 +
1996 +#define MTK_PHY_RG_DEV1E_REG238 0x238
1997 +#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
1998 +#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
1999 +
2000 +#define MTK_PHY_RG_DEV1E_REG239 0x239
2001 +#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
2002 +#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
2003 +
2004 +#define MTK_PHY_RG_DEV1E_REG27C 0x27c
2005 +#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
2006 +#define MTK_PHY_RG_DEV1E_REG27D 0x27d
2007 +#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
2008 +
2009 +#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
2010 +#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
2011 +#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
2012 +
2013 +#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
2014 +#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
2015 +#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
2016 +#define MTK_PHY_LPI_TR_READY BIT(9)
2017 +#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
2018 +
2019 +#define MTK_PHY_RG_DEV1E_REG323 0x323
2020 +#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
2021 +#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
2022 +
2023 +#define MTK_PHY_RG_DEV1E_REG324 0x324
2024 +#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
2025 +#define MTK_PHY_SMI_DET_MAX_EN BIT(8)
2026 +
2027 +#define MTK_PHY_RG_DEV1E_REG326 0x326
2028 +#define MTK_PHY_LPI_MODE_SD_ON BIT(0)
2029 +#define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
2030 +#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
2031 +#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
2032 +#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
2033 +
2034 +#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
2035 +#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
2036 +
2037 +#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
2038 +#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
2039 +#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
2040 +#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
2041 +
2042 +/* Registers on MDIO_MMD_VEND2 */
2043 +#define MTK_PHY_LED0_ON_CTRL 0x24
2044 +#define MTK_PHY_LED1_ON_CTRL 0x26
2045 +#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
2046 +#define MTK_PHY_LED_ON_LINK1000 BIT(0)
2047 +#define MTK_PHY_LED_ON_LINK100 BIT(1)
2048 +#define MTK_PHY_LED_ON_LINK10 BIT(2)
2049 +#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
2050 + MTK_PHY_LED_ON_LINK100 |\
2051 + MTK_PHY_LED_ON_LINK1000)
2052 +#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
2053 +#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
2054 +#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
2055 +#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
2056 +#define MTK_PHY_LED_ON_POLARITY BIT(14)
2057 +#define MTK_PHY_LED_ON_ENABLE BIT(15)
2058 +
2059 +#define MTK_PHY_LED0_BLINK_CTRL 0x25
2060 +#define MTK_PHY_LED1_BLINK_CTRL 0x27
2061 +#define MTK_PHY_LED_BLINK_1000TX BIT(0)
2062 +#define MTK_PHY_LED_BLINK_1000RX BIT(1)
2063 +#define MTK_PHY_LED_BLINK_100TX BIT(2)
2064 +#define MTK_PHY_LED_BLINK_100RX BIT(3)
2065 +#define MTK_PHY_LED_BLINK_10TX BIT(4)
2066 +#define MTK_PHY_LED_BLINK_10RX BIT(5)
2067 +#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
2068 + MTK_PHY_LED_BLINK_100RX |\
2069 + MTK_PHY_LED_BLINK_1000RX)
2070 +#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
2071 + MTK_PHY_LED_BLINK_100TX |\
2072 + MTK_PHY_LED_BLINK_1000TX)
2073 +#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
2074 +#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
2075 +#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
2076 +#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
2077 +
2078 +#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
2079 +
2080 +#define MTK_PHY_RG_BG_RASEL 0x115
2081 +#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
2082 +
2083 +/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */
2084 +#define RG_GPIO_MISC_TPBANK0 0x6f0
2085 +#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
2086 +
2087 +/* These macro privides efuse parsing for internal phy. */
2088 +#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
2089 +#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
2090 +#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
2091 +#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
2092 +#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
2093 +
2094 +#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
2095 +#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
2096 +#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
2097 +#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
2098 +#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
2099 +
2100 +#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
2101 +#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
2102 +
2103 +#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
2104 +#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
2105 +
2106 +enum {
2107 + NO_PAIR,
2108 + PAIR_A,
2109 + PAIR_B,
2110 + PAIR_C,
2111 + PAIR_D,
2112 +};
2113 +
2114 +enum calibration_mode {
2115 + EFUSE_K,
2116 + SW_K
2117 +};
2118 +
2119 +enum CAL_ITEM {
2120 + REXT,
2121 + TX_OFFSET,
2122 + TX_AMP,
2123 + TX_R50,
2124 + TX_VCM
2125 +};
2126 +
2127 +enum CAL_MODE {
2128 + EFUSE_M,
2129 + SW_M
2130 +};
2131 +
2132 +#define MTK_PHY_LED_STATE_FORCE_ON 0
2133 +#define MTK_PHY_LED_STATE_FORCE_BLINK 1
2134 +#define MTK_PHY_LED_STATE_NETDEV 2
2135 +
2136 +struct mtk_socphy_priv {
2137 + unsigned long led_state;
2138 +};
2139 +
2140 +struct mtk_socphy_shared {
2141 + u32 boottrap;
2142 + struct mtk_socphy_priv priv[4];
2143 +};
2144 +
2145 +static int mtk_socphy_read_page(struct phy_device *phydev)
2146 +{
2147 + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
2148 +}
2149 +
2150 +static int mtk_socphy_write_page(struct phy_device *phydev, int page)
2151 +{
2152 + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
2153 +}
2154 +
2155 +/* One calibration cycle consists of:
2156 + * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
2157 + * until AD_CAL_COMP is ready to output calibration result.
2158 + * 2.Wait until DA_CAL_CLK is available.
2159 + * 3.Fetch AD_CAL_COMP_OUT.
2160 + */
2161 +static int cal_cycle(struct phy_device *phydev, int devad,
2162 + u32 regnum, u16 mask, u16 cal_val)
2163 +{
2164 + int reg_val;
2165 + int ret;
2166 +
2167 + phy_modify_mmd(phydev, devad, regnum,
2168 + mask, cal_val);
2169 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
2170 + MTK_PHY_DA_CALIN_FLAG);
2171 +
2172 + ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2173 + MTK_PHY_RG_AD_CAL_CLK, reg_val,
2174 + reg_val & MTK_PHY_DA_CAL_CLK, 500,
2175 + ANALOG_INTERNAL_OPERATION_MAX_US,
2176 + false);
2177 + if (ret) {
2178 + phydev_err(phydev, "Calibration cycle timeout\n");
2179 + return ret;
2180 + }
2181 +
2182 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN,
2183 + MTK_PHY_DA_CALIN_FLAG);
2184 + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP);
2185 + if (ret < 0)
2186 + return ret;
2187 + ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret);
2188 + phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
2189 +
2190 + return ret;
2191 +}
2192 +
2193 +static int rext_fill_result(struct phy_device *phydev, u16 *buf)
2194 +{
2195 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5,
2196 + MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8);
2197 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL,
2198 + MTK_PHY_RG_BG_RASEL_MASK, buf[1]);
2199 +
2200 + return 0;
2201 +}
2202 +
2203 +static int rext_cal_efuse(struct phy_device *phydev, u32 *buf)
2204 +{
2205 + u16 rext_cal_val[2];
2206 +
2207 + rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]);
2208 + rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]);
2209 + rext_fill_result(phydev, rext_cal_val);
2210 +
2211 + return 0;
2212 +}
2213 +
2214 +static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf)
2215 +{
2216 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
2217 + MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8);
2218 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B,
2219 + MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]);
2220 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
2221 + MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8);
2222 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D,
2223 + MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]);
2224 +
2225 + return 0;
2226 +}
2227 +
2228 +static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf)
2229 +{
2230 + u16 tx_offset_cal_val[4];
2231 +
2232 + tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]);
2233 + tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]);
2234 + tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]);
2235 + tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]);
2236 +
2237 + tx_offset_fill_result(phydev, tx_offset_cal_val);
2238 +
2239 + return 0;
2240 +}
2241 +
2242 +static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
2243 +{
2244 + const int vals_9481[16] = { 10, 6, 6, 10,
2245 + 10, 6, 6, 10,
2246 + 10, 6, 6, 10,
2247 + 10, 6, 6, 10 };
2248 + const int vals_9461[16] = { 7, 1, 4, 7,
2249 + 7, 1, 4, 7,
2250 + 7, 1, 4, 7,
2251 + 7, 1, 4, 7 };
2252 + int bias[16] = {};
2253 + int i;
2254 +
2255 + switch (phydev->drv->phy_id) {
2256 + case MTK_GPHY_ID_MT7981:
2257 + /* We add some calibration to efuse values
2258 + * due to board level influence.
2259 + * GBE: +7, TBT: +1, HBT: +4, TST: +7
2260 + */
2261 + memcpy(bias, (const void *)vals_9461, sizeof(bias));
2262 + break;
2263 + case MTK_GPHY_ID_MT7988:
2264 + memcpy(bias, (const void *)vals_9481, sizeof(bias));
2265 + break;
2266 + }
2267 +
2268 + /* Prevent overflow */
2269 + for (i = 0; i < 12; i++) {
2270 + if (buf[i >> 2] + bias[i] > 63) {
2271 + buf[i >> 2] = 63;
2272 + bias[i] = 0;
2273 + }
2274 + }
2275 +
2276 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
2277 + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
2278 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK,
2279 + buf[0] + bias[0]));
2280 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG,
2281 + MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
2282 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK,
2283 + buf[0] + bias[1]));
2284 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
2285 + MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
2286 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK,
2287 + buf[0] + bias[2]));
2288 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2,
2289 + MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
2290 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK,
2291 + buf[0] + bias[3]));
2292 +
2293 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
2294 + MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
2295 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK,
2296 + buf[1] + bias[4]));
2297 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1,
2298 + MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
2299 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK,
2300 + buf[1] + bias[5]));
2301 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
2302 + MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
2303 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK,
2304 + buf[1] + bias[6]));
2305 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2,
2306 + MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
2307 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK,
2308 + buf[1] + bias[7]));
2309 +
2310 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
2311 + MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
2312 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK,
2313 + buf[2] + bias[8]));
2314 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1,
2315 + MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
2316 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK,
2317 + buf[2] + bias[9]));
2318 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
2319 + MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
2320 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK,
2321 + buf[2] + bias[10]));
2322 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2,
2323 + MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
2324 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK,
2325 + buf[2] + bias[11]));
2326 +
2327 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
2328 + MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
2329 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK,
2330 + buf[3] + bias[12]));
2331 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1,
2332 + MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
2333 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK,
2334 + buf[3] + bias[13]));
2335 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
2336 + MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
2337 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK,
2338 + buf[3] + bias[14]));
2339 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2,
2340 + MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
2341 + FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK,
2342 + buf[3] + bias[15]));
2343 +
2344 + return 0;
2345 +}
2346 +
2347 +static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf)
2348 +{
2349 + u16 tx_amp_cal_val[4];
2350 +
2351 + tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]);
2352 + tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]);
2353 + tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]);
2354 + tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]);
2355 + tx_amp_fill_result(phydev, tx_amp_cal_val);
2356 +
2357 + return 0;
2358 +}
2359 +
2360 +static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val,
2361 + u8 txg_calen_x)
2362 +{
2363 + int bias = 0;
2364 + u16 reg, val;
2365 +
2366 + if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
2367 + bias = -1;
2368 +
2369 + val = clamp_val(bias + tx_r50_cal_val, 0, 63);
2370 +
2371 + switch (txg_calen_x) {
2372 + case PAIR_A:
2373 + reg = MTK_PHY_DA_TX_R50_PAIR_A;
2374 + break;
2375 + case PAIR_B:
2376 + reg = MTK_PHY_DA_TX_R50_PAIR_B;
2377 + break;
2378 + case PAIR_C:
2379 + reg = MTK_PHY_DA_TX_R50_PAIR_C;
2380 + break;
2381 + case PAIR_D:
2382 + reg = MTK_PHY_DA_TX_R50_PAIR_D;
2383 + break;
2384 + default:
2385 + return -EINVAL;
2386 + }
2387 +
2388 + phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8);
2389 +
2390 + return 0;
2391 +}
2392 +
2393 +static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf,
2394 + u8 txg_calen_x)
2395 +{
2396 + u16 tx_r50_cal_val;
2397 +
2398 + switch (txg_calen_x) {
2399 + case PAIR_A:
2400 + tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]);
2401 + break;
2402 + case PAIR_B:
2403 + tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]);
2404 + break;
2405 + case PAIR_C:
2406 + tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]);
2407 + break;
2408 + case PAIR_D:
2409 + tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]);
2410 + break;
2411 + default:
2412 + return -EINVAL;
2413 + }
2414 + tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x);
2415 +
2416 + return 0;
2417 +}
2418 +
2419 +static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x)
2420 +{
2421 + u8 lower_idx, upper_idx, txreserve_val;
2422 + u8 lower_ret, upper_ret;
2423 + int ret;
2424 +
2425 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2426 + MTK_PHY_RG_ANA_CALEN);
2427 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2428 + MTK_PHY_RG_CAL_CKINV);
2429 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
2430 + MTK_PHY_RG_TXVOS_CALEN);
2431 +
2432 + switch (rg_txreserve_x) {
2433 + case PAIR_A:
2434 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2435 + MTK_PHY_RG_DASN_DAC_IN0_A,
2436 + MTK_PHY_DASN_DAC_IN0_A_MASK);
2437 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2438 + MTK_PHY_RG_DASN_DAC_IN1_A,
2439 + MTK_PHY_DASN_DAC_IN1_A_MASK);
2440 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2441 + MTK_PHY_RG_ANA_CAL_RG0,
2442 + MTK_PHY_RG_ZCALEN_A);
2443 + break;
2444 + case PAIR_B:
2445 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2446 + MTK_PHY_RG_DASN_DAC_IN0_B,
2447 + MTK_PHY_DASN_DAC_IN0_B_MASK);
2448 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2449 + MTK_PHY_RG_DASN_DAC_IN1_B,
2450 + MTK_PHY_DASN_DAC_IN1_B_MASK);
2451 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2452 + MTK_PHY_RG_ANA_CAL_RG1,
2453 + MTK_PHY_RG_ZCALEN_B);
2454 + break;
2455 + case PAIR_C:
2456 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2457 + MTK_PHY_RG_DASN_DAC_IN0_C,
2458 + MTK_PHY_DASN_DAC_IN0_C_MASK);
2459 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2460 + MTK_PHY_RG_DASN_DAC_IN1_C,
2461 + MTK_PHY_DASN_DAC_IN1_C_MASK);
2462 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2463 + MTK_PHY_RG_ANA_CAL_RG1,
2464 + MTK_PHY_RG_ZCALEN_C);
2465 + break;
2466 + case PAIR_D:
2467 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2468 + MTK_PHY_RG_DASN_DAC_IN0_D,
2469 + MTK_PHY_DASN_DAC_IN0_D_MASK);
2470 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2471 + MTK_PHY_RG_DASN_DAC_IN1_D,
2472 + MTK_PHY_DASN_DAC_IN1_D_MASK);
2473 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2474 + MTK_PHY_RG_ANA_CAL_RG1,
2475 + MTK_PHY_RG_ZCALEN_D);
2476 + break;
2477 + default:
2478 + ret = -EINVAL;
2479 + goto restore;
2480 + }
2481 +
2482 + lower_idx = TXRESERVE_MIN;
2483 + upper_idx = TXRESERVE_MAX;
2484 +
2485 + phydev_dbg(phydev, "Start TX-VCM SW cal.\n");
2486 + while ((upper_idx - lower_idx) > 1) {
2487 + txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2);
2488 + ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
2489 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2490 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2491 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2492 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2493 + txreserve_val << 12 | txreserve_val << 8 |
2494 + txreserve_val << 4 | txreserve_val);
2495 + if (ret == 1) {
2496 + upper_idx = txreserve_val;
2497 + upper_ret = ret;
2498 + } else if (ret == 0) {
2499 + lower_idx = txreserve_val;
2500 + lower_ret = ret;
2501 + } else {
2502 + goto restore;
2503 + }
2504 + }
2505 +
2506 + if (lower_idx == TXRESERVE_MIN) {
2507 + lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
2508 + MTK_PHY_RXADC_CTRL_RG9,
2509 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2510 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2511 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2512 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2513 + lower_idx << 12 | lower_idx << 8 |
2514 + lower_idx << 4 | lower_idx);
2515 + ret = lower_ret;
2516 + } else if (upper_idx == TXRESERVE_MAX) {
2517 + upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1,
2518 + MTK_PHY_RXADC_CTRL_RG9,
2519 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2520 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2521 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2522 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2523 + upper_idx << 12 | upper_idx << 8 |
2524 + upper_idx << 4 | upper_idx);
2525 + ret = upper_ret;
2526 + }
2527 + if (ret < 0)
2528 + goto restore;
2529 +
2530 + /* We calibrate TX-VCM in different logic. Check upper index and then
2531 + * lower index. If this calibration is valid, apply lower index's
2532 + * result.
2533 + */
2534 + ret = upper_ret - lower_ret;
2535 + if (ret == 1) {
2536 + ret = 0;
2537 + /* Make sure we use upper_idx in our calibration system */
2538 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
2539 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2540 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2541 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2542 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2543 + upper_idx << 12 | upper_idx << 8 |
2544 + upper_idx << 4 | upper_idx);
2545 + phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx);
2546 + } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 &&
2547 + lower_ret == 1) {
2548 + ret = 0;
2549 + cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9,
2550 + MTK_PHY_DA_RX_PSBN_TBT_MASK |
2551 + MTK_PHY_DA_RX_PSBN_HBT_MASK |
2552 + MTK_PHY_DA_RX_PSBN_GBE_MASK |
2553 + MTK_PHY_DA_RX_PSBN_LP_MASK,
2554 + lower_idx << 12 | lower_idx << 8 |
2555 + lower_idx << 4 | lower_idx);
2556 + phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n",
2557 + lower_idx);
2558 + } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 &&
2559 + lower_ret == 0) {
2560 + ret = 0;
2561 + phydev_warn(phydev,
2562 + "TX-VCM SW cal result at high margin 0x%x\n",
2563 + upper_idx);
2564 + } else {
2565 + ret = -EINVAL;
2566 + }
2567 +
2568 +restore:
2569 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2570 + MTK_PHY_RG_ANA_CALEN);
2571 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
2572 + MTK_PHY_RG_TXVOS_CALEN);
2573 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0,
2574 + MTK_PHY_RG_ZCALEN_A);
2575 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1,
2576 + MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C |
2577 + MTK_PHY_RG_ZCALEN_D);
2578 +
2579 + return ret;
2580 +}
2581 +
2582 +static void mt798x_phy_common_finetune(struct phy_device *phydev)
2583 +{
2584 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2585 + /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
2586 + __phy_write(phydev, 0x11, 0xc71);
2587 + __phy_write(phydev, 0x12, 0xc);
2588 + __phy_write(phydev, 0x10, 0x8fae);
2589 +
2590 + /* EnabRandUpdTrig = 1 */
2591 + __phy_write(phydev, 0x11, 0x2f00);
2592 + __phy_write(phydev, 0x12, 0xe);
2593 + __phy_write(phydev, 0x10, 0x8fb0);
2594 +
2595 + /* NormMseLoThresh = 85 */
2596 + __phy_write(phydev, 0x11, 0x55a0);
2597 + __phy_write(phydev, 0x12, 0x0);
2598 + __phy_write(phydev, 0x10, 0x83aa);
2599 +
2600 + /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
2601 + __phy_write(phydev, 0x11, 0x240);
2602 + __phy_write(phydev, 0x12, 0x0);
2603 + __phy_write(phydev, 0x10, 0x9680);
2604 +
2605 + /* TrFreeze = 0 (mt7988 default) */
2606 + __phy_write(phydev, 0x11, 0x0);
2607 + __phy_write(phydev, 0x12, 0x0);
2608 + __phy_write(phydev, 0x10, 0x9686);
2609 +
2610 + /* SSTrKp100 = 5 */
2611 + /* SSTrKf100 = 6 */
2612 + /* SSTrKp1000Mas = 5 */
2613 + /* SSTrKf1000Mas = 6 */
2614 + /* SSTrKp1000Slv = 5 */
2615 + /* SSTrKf1000Slv = 6 */
2616 + __phy_write(phydev, 0x11, 0xbaef);
2617 + __phy_write(phydev, 0x12, 0x2e);
2618 + __phy_write(phydev, 0x10, 0x968c);
2619 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2620 +}
2621 +
2622 +static void mt7981_phy_finetune(struct phy_device *phydev)
2623 +{
2624 + u16 val[8] = { 0x01ce, 0x01c1,
2625 + 0x020f, 0x0202,
2626 + 0x03d0, 0x03c0,
2627 + 0x0013, 0x0005 };
2628 + int i, k;
2629 +
2630 + /* 100M eye finetune:
2631 + * Keep middle level of TX MLT3 shapper as default.
2632 + * Only change TX MLT3 overshoot level here.
2633 + */
2634 + for (k = 0, i = 1; i < 12; i++) {
2635 + if (i % 3 == 0)
2636 + continue;
2637 + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
2638 + }
2639 +
2640 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2641 + /* ResetSyncOffset = 6 */
2642 + __phy_write(phydev, 0x11, 0x600);
2643 + __phy_write(phydev, 0x12, 0x0);
2644 + __phy_write(phydev, 0x10, 0x8fc0);
2645 +
2646 + /* VgaDecRate = 1 */
2647 + __phy_write(phydev, 0x11, 0x4c2a);
2648 + __phy_write(phydev, 0x12, 0x3e);
2649 + __phy_write(phydev, 0x10, 0x8fa4);
2650 +
2651 + /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
2652 + * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
2653 + */
2654 + __phy_write(phydev, 0x11, 0xd10a);
2655 + __phy_write(phydev, 0x12, 0x34);
2656 + __phy_write(phydev, 0x10, 0x8f82);
2657 +
2658 + /* VcoSlicerThreshBitsHigh */
2659 + __phy_write(phydev, 0x11, 0x5555);
2660 + __phy_write(phydev, 0x12, 0x55);
2661 + __phy_write(phydev, 0x10, 0x8ec0);
2662 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2663 +
2664 + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
2665 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
2666 + MTK_PHY_TR_OPEN_LOOP_EN_MASK |
2667 + MTK_PHY_LPF_X_AVERAGE_MASK,
2668 + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
2669 +
2670 + /* rg_tr_lpf_cnt_val = 512 */
2671 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200);
2672 +
2673 + /* IIR2 related */
2674 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82);
2675 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0);
2676 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103);
2677 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0);
2678 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82);
2679 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0);
2680 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177);
2681 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3);
2682 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82);
2683 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe);
2684 +
2685 + /* FFE peaking */
2686 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C,
2687 + MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8);
2688 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D,
2689 + MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e);
2690 +
2691 + /* Disable LDO pump */
2692 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0);
2693 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0);
2694 + /* Adjust LDO output voltage */
2695 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
2696 +}
2697 +
2698 +static void mt7988_phy_finetune(struct phy_device *phydev)
2699 +{
2700 + u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
2701 + 0x020d, 0x0206, 0x0384, 0x03d0,
2702 + 0x03c6, 0x030a, 0x0011, 0x0005 };
2703 + int i;
2704 +
2705 + /* Set default MLT3 shaper first */
2706 + for (i = 0; i < 12; i++)
2707 + phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]);
2708 +
2709 + /* TCT finetune */
2710 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
2711 +
2712 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2713 + /* ResetSyncOffset = 5 */
2714 + __phy_write(phydev, 0x11, 0x500);
2715 + __phy_write(phydev, 0x12, 0x0);
2716 + __phy_write(phydev, 0x10, 0x8fc0);
2717 +
2718 + /* VgaDecRate is 1 at default on mt7988 */
2719 +
2720 + /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
2721 + * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
2722 + */
2723 + __phy_write(phydev, 0x11, 0xb90a);
2724 + __phy_write(phydev, 0x12, 0x6f);
2725 + __phy_write(phydev, 0x10, 0x8f82);
2726 +
2727 + /* RemAckCntLimitCtrl = 1 */
2728 + __phy_write(phydev, 0x11, 0xfbba);
2729 + __phy_write(phydev, 0x12, 0xc3);
2730 + __phy_write(phydev, 0x10, 0x87f8);
2731 +
2732 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2733 +
2734 + /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
2735 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
2736 + MTK_PHY_TR_OPEN_LOOP_EN_MASK |
2737 + MTK_PHY_LPF_X_AVERAGE_MASK,
2738 + BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
2739 +
2740 + /* rg_tr_lpf_cnt_val = 1023 */
2741 + phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
2742 +}
2743 +
2744 +static void mt798x_phy_eee(struct phy_device *phydev)
2745 +{
2746 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
2747 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120,
2748 + MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK |
2749 + MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK,
2750 + FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) |
2751 + FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14));
2752 +
2753 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
2754 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
2755 + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2756 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2757 + 0xff));
2758 +
2759 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2760 + MTK_PHY_RG_TESTMUX_ADC_CTRL,
2761 + MTK_PHY_RG_TXEN_DIG_MASK);
2762 +
2763 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2764 + MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY);
2765 +
2766 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
2767 + MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN);
2768 +
2769 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238,
2770 + MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK |
2771 + MTK_PHY_LPI_SLV_SEND_TX_EN,
2772 + FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
2773 +
2774 + /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
2775 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
2776 + MTK_PHY_LPI_TXPCS_LOC_RCV);
2777 +
2778 + /* This also fixes some IoT issues, such as CH340 */
2779 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
2780 + MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
2781 + FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
2782 + FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13));
2783 +
2784 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1,
2785 + MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
2786 + FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK,
2787 + 0x33) |
2788 + MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY |
2789 + MTK_PHY_LPI_VCO_EEE_STG0_EN);
2790 +
2791 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323,
2792 + MTK_PHY_EEE_WAKE_MAS_INT_DC |
2793 + MTK_PHY_EEE_WAKE_SLV_INT_DC);
2794 +
2795 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324,
2796 + MTK_PHY_SMI_DETCNT_MAX_MASK,
2797 + FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) |
2798 + MTK_PHY_SMI_DET_MAX_EN);
2799 +
2800 + phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326,
2801 + MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT |
2802 + MTK_PHY_TREC_UPDATE_ENAB_CLR |
2803 + MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF |
2804 + MTK_PHY_TR_READY_SKIP_AFE_WAKEUP);
2805 +
2806 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
2807 + /* Regsigdet_sel_1000 = 0 */
2808 + __phy_write(phydev, 0x11, 0xb);
2809 + __phy_write(phydev, 0x12, 0x0);
2810 + __phy_write(phydev, 0x10, 0x9690);
2811 +
2812 + /* REG_EEE_st2TrKf1000 = 2 */
2813 + __phy_write(phydev, 0x11, 0x114f);
2814 + __phy_write(phydev, 0x12, 0x2);
2815 + __phy_write(phydev, 0x10, 0x969a);
2816 +
2817 + /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
2818 + __phy_write(phydev, 0x11, 0x3028);
2819 + __phy_write(phydev, 0x12, 0x0);
2820 + __phy_write(phydev, 0x10, 0x969e);
2821 +
2822 + /* RegEEE_slv_wake_int_timer_tar = 8 */
2823 + __phy_write(phydev, 0x11, 0x5010);
2824 + __phy_write(phydev, 0x12, 0x0);
2825 + __phy_write(phydev, 0x10, 0x96a0);
2826 +
2827 + /* RegEEE_trfreeze_timer2 = 586 */
2828 + __phy_write(phydev, 0x11, 0x24a);
2829 + __phy_write(phydev, 0x12, 0x0);
2830 + __phy_write(phydev, 0x10, 0x96a8);
2831 +
2832 + /* RegEEE100Stg1_tar = 16 */
2833 + __phy_write(phydev, 0x11, 0x3210);
2834 + __phy_write(phydev, 0x12, 0x0);
2835 + __phy_write(phydev, 0x10, 0x96b8);
2836 +
2837 + /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
2838 + __phy_write(phydev, 0x11, 0x1463);
2839 + __phy_write(phydev, 0x12, 0x0);
2840 + __phy_write(phydev, 0x10, 0x96ca);
2841 +
2842 + /* DfeTailEnableVgaThresh1000 = 27 */
2843 + __phy_write(phydev, 0x11, 0x36);
2844 + __phy_write(phydev, 0x12, 0x0);
2845 + __phy_write(phydev, 0x10, 0x8f80);
2846 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2847 +
2848 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3);
2849 + __phy_modify(phydev, MTK_PHY_LPI_REG_14,
2850 + MTK_PHY_LPI_WAKE_TIMER_1000_MASK,
2851 + FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c));
2852 +
2853 + __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK,
2854 + FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc));
2855 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
2856 +
2857 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
2858 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122,
2859 + MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2860 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK,
2861 + 0xff));
2862 +}
2863 +
2864 +static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item,
2865 + u8 start_pair, u8 end_pair)
2866 +{
2867 + u8 pair_n;
2868 + int ret;
2869 +
2870 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
2871 + /* TX_OFFSET & TX_AMP have no SW calibration. */
2872 + switch (cal_item) {
2873 + case TX_VCM:
2874 + ret = tx_vcm_cal_sw(phydev, pair_n);
2875 + break;
2876 + default:
2877 + return -EINVAL;
2878 + }
2879 + if (ret)
2880 + return ret;
2881 + }
2882 + return 0;
2883 +}
2884 +
2885 +static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item,
2886 + u8 start_pair, u8 end_pair, u32 *buf)
2887 +{
2888 + u8 pair_n;
2889 + int ret;
2890 +
2891 + for (pair_n = start_pair; pair_n <= end_pair; pair_n++) {
2892 + /* TX_VCM has no efuse calibration. */
2893 + switch (cal_item) {
2894 + case REXT:
2895 + ret = rext_cal_efuse(phydev, buf);
2896 + break;
2897 + case TX_OFFSET:
2898 + ret = tx_offset_cal_efuse(phydev, buf);
2899 + break;
2900 + case TX_AMP:
2901 + ret = tx_amp_cal_efuse(phydev, buf);
2902 + break;
2903 + case TX_R50:
2904 + ret = tx_r50_cal_efuse(phydev, buf, pair_n);
2905 + break;
2906 + default:
2907 + return -EINVAL;
2908 + }
2909 + if (ret)
2910 + return ret;
2911 + }
2912 +
2913 + return 0;
2914 +}
2915 +
2916 +static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item,
2917 + enum CAL_MODE cal_mode, u8 start_pair,
2918 + u8 end_pair, u32 *buf)
2919 +{
2920 + int ret;
2921 +
2922 + switch (cal_mode) {
2923 + case EFUSE_M:
2924 + ret = cal_efuse(phydev, cal_item, start_pair,
2925 + end_pair, buf);
2926 + break;
2927 + case SW_M:
2928 + ret = cal_sw(phydev, cal_item, start_pair, end_pair);
2929 + break;
2930 + default:
2931 + return -EINVAL;
2932 + }
2933 +
2934 + if (ret) {
2935 + phydev_err(phydev, "cal %d failed\n", cal_item);
2936 + return -EIO;
2937 + }
2938 +
2939 + return 0;
2940 +}
2941 +
2942 +static int mt798x_phy_calibration(struct phy_device *phydev)
2943 +{
2944 + struct nvmem_cell *cell;
2945 + int ret = 0;
2946 + size_t len;
2947 + u32 *buf;
2948 +
2949 + cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
2950 + if (IS_ERR(cell)) {
2951 + if (PTR_ERR(cell) == -EPROBE_DEFER)
2952 + return PTR_ERR(cell);
2953 + return 0;
2954 + }
2955 +
2956 + buf = (u32 *)nvmem_cell_read(cell, &len);
2957 + if (IS_ERR(buf))
2958 + return PTR_ERR(buf);
2959 + nvmem_cell_put(cell);
2960 +
2961 + if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) {
2962 + phydev_err(phydev, "invalid efuse data\n");
2963 + ret = -EINVAL;
2964 + goto out;
2965 + }
2966 +
2967 + ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf);
2968 + if (ret)
2969 + goto out;
2970 + ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf);
2971 + if (ret)
2972 + goto out;
2973 + ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf);
2974 + if (ret)
2975 + goto out;
2976 + ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf);
2977 + if (ret)
2978 + goto out;
2979 + ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf);
2980 + if (ret)
2981 + goto out;
2982 +
2983 +out:
2984 + kfree(buf);
2985 + return ret;
2986 +}
2987 +
2988 +static int mt798x_phy_config_init(struct phy_device *phydev)
2989 +{
2990 + switch (phydev->drv->phy_id) {
2991 + case MTK_GPHY_ID_MT7981:
2992 + mt7981_phy_finetune(phydev);
2993 + break;
2994 + case MTK_GPHY_ID_MT7988:
2995 + mt7988_phy_finetune(phydev);
2996 + break;
2997 + }
2998 +
2999 + mt798x_phy_common_finetune(phydev);
3000 + mt798x_phy_eee(phydev);
3001 +
3002 + return mt798x_phy_calibration(phydev);
3003 +}
3004 +
3005 +static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
3006 + bool on)
3007 +{
3008 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
3009 + struct mtk_socphy_priv *priv = phydev->priv;
3010 + bool changed;
3011 +
3012 + if (on)
3013 + changed = !test_and_set_bit(bit_on, &priv->led_state);
3014 + else
3015 + changed = !!test_and_clear_bit(bit_on, &priv->led_state);
3016 +
3017 + changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
3018 + (index ? 16 : 0), &priv->led_state);
3019 + if (changed)
3020 + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
3021 + MTK_PHY_LED1_ON_CTRL :
3022 + MTK_PHY_LED0_ON_CTRL,
3023 + MTK_PHY_LED_ON_MASK,
3024 + on ? MTK_PHY_LED_ON_FORCE_ON : 0);
3025 + else
3026 + return 0;
3027 +}
3028 +
3029 +static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
3030 + bool blinking)
3031 +{
3032 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
3033 + (index ? 16 : 0);
3034 + struct mtk_socphy_priv *priv = phydev->priv;
3035 + bool changed;
3036 +
3037 + if (blinking)
3038 + changed = !test_and_set_bit(bit_blink, &priv->led_state);
3039 + else
3040 + changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
3041 +
3042 + changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
3043 + (index ? 16 : 0), &priv->led_state);
3044 + if (changed)
3045 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
3046 + MTK_PHY_LED1_BLINK_CTRL :
3047 + MTK_PHY_LED0_BLINK_CTRL,
3048 + blinking ?
3049 + MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
3050 + else
3051 + return 0;
3052 +}
3053 +
3054 +static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
3055 + unsigned long *delay_on,
3056 + unsigned long *delay_off)
3057 +{
3058 + bool blinking = false;
3059 + int err = 0;
3060 +
3061 + if (index > 1)
3062 + return -EINVAL;
3063 +
3064 + if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
3065 + blinking = true;
3066 + *delay_on = 50;
3067 + *delay_off = 50;
3068 + }
3069 +
3070 + err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
3071 + if (err)
3072 + return err;
3073 +
3074 + return mt798x_phy_hw_led_on_set(phydev, index, false);
3075 +}
3076 +
3077 +static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
3078 + u8 index, enum led_brightness value)
3079 +{
3080 + int err;
3081 +
3082 + err = mt798x_phy_hw_led_blink_set(phydev, index, false);
3083 + if (err)
3084 + return err;
3085 +
3086 + return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
3087 +}
3088 +
3089 +static const unsigned long supported_triggers =
3090 + BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
3091 + BIT(TRIGGER_NETDEV_HALF_DUPLEX) |
3092 + BIT(TRIGGER_NETDEV_LINK) |
3093 + BIT(TRIGGER_NETDEV_LINK_10) |
3094 + BIT(TRIGGER_NETDEV_LINK_100) |
3095 + BIT(TRIGGER_NETDEV_LINK_1000) |
3096 + BIT(TRIGGER_NETDEV_RX) |
3097 + BIT(TRIGGER_NETDEV_TX);
3098 +
3099 +static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
3100 + unsigned long rules)
3101 +{
3102 + if (index > 1)
3103 + return -EINVAL;
3104 +
3105 + /* All combinations of the supported triggers are allowed */
3106 + if (rules & ~supported_triggers)
3107 + return -EOPNOTSUPP;
3108 +
3109 + return 0;
3110 +};
3111 +
3112 +static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
3113 + unsigned long *rules)
3114 +{
3115 + unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
3116 + (index ? 16 : 0);
3117 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
3118 + unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
3119 + struct mtk_socphy_priv *priv = phydev->priv;
3120 + int on, blink;
3121 +
3122 + if (index > 1)
3123 + return -EINVAL;
3124 +
3125 + on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
3126 + index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
3127 +
3128 + if (on < 0)
3129 + return -EIO;
3130 +
3131 + blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
3132 + index ? MTK_PHY_LED1_BLINK_CTRL :
3133 + MTK_PHY_LED0_BLINK_CTRL);
3134 + if (blink < 0)
3135 + return -EIO;
3136 +
3137 + if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
3138 + MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
3139 + (blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
3140 + set_bit(bit_netdev, &priv->led_state);
3141 + else
3142 + clear_bit(bit_netdev, &priv->led_state);
3143 +
3144 + if (on & MTK_PHY_LED_ON_FORCE_ON)
3145 + set_bit(bit_on, &priv->led_state);
3146 + else
3147 + clear_bit(bit_on, &priv->led_state);
3148 +
3149 + if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
3150 + set_bit(bit_blink, &priv->led_state);
3151 + else
3152 + clear_bit(bit_blink, &priv->led_state);
3153 +
3154 + if (!rules)
3155 + return 0;
3156 +
3157 + if (on & MTK_PHY_LED_ON_LINK)
3158 + *rules |= BIT(TRIGGER_NETDEV_LINK);
3159 +
3160 + if (on & MTK_PHY_LED_ON_LINK10)
3161 + *rules |= BIT(TRIGGER_NETDEV_LINK_10);
3162 +
3163 + if (on & MTK_PHY_LED_ON_LINK100)
3164 + *rules |= BIT(TRIGGER_NETDEV_LINK_100);
3165 +
3166 + if (on & MTK_PHY_LED_ON_LINK1000)
3167 + *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
3168 +
3169 + if (on & MTK_PHY_LED_ON_FDX)
3170 + *rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
3171 +
3172 + if (on & MTK_PHY_LED_ON_HDX)
3173 + *rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
3174 +
3175 + if (blink & MTK_PHY_LED_BLINK_RX)
3176 + *rules |= BIT(TRIGGER_NETDEV_RX);
3177 +
3178 + if (blink & MTK_PHY_LED_BLINK_TX)
3179 + *rules |= BIT(TRIGGER_NETDEV_TX);
3180 +
3181 + return 0;
3182 +};
3183 +
3184 +static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
3185 + unsigned long rules)
3186 +{
3187 + unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
3188 + struct mtk_socphy_priv *priv = phydev->priv;
3189 + u16 on = 0, blink = 0;
3190 + int ret;
3191 +
3192 + if (index > 1)
3193 + return -EINVAL;
3194 +
3195 + if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
3196 + on |= MTK_PHY_LED_ON_FDX;
3197 +
3198 + if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
3199 + on |= MTK_PHY_LED_ON_HDX;
3200 +
3201 + if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
3202 + on |= MTK_PHY_LED_ON_LINK10;
3203 +
3204 + if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
3205 + on |= MTK_PHY_LED_ON_LINK100;
3206 +
3207 + if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
3208 + on |= MTK_PHY_LED_ON_LINK1000;
3209 +
3210 + if (rules & BIT(TRIGGER_NETDEV_RX)) {
3211 + blink |= (on & MTK_PHY_LED_ON_LINK) ?
3212 + (((on & MTK_PHY_LED_ON_LINK10) ?
3213 + MTK_PHY_LED_BLINK_10RX : 0) |
3214 + ((on & MTK_PHY_LED_ON_LINK100) ?
3215 + MTK_PHY_LED_BLINK_100RX : 0) |
3216 + ((on & MTK_PHY_LED_ON_LINK1000) ?
3217 + MTK_PHY_LED_BLINK_1000RX : 0)) :
3218 + MTK_PHY_LED_BLINK_RX;
3219 + }
3220 +
3221 + if (rules & BIT(TRIGGER_NETDEV_TX)) {
3222 + blink |= (on & MTK_PHY_LED_ON_LINK) ?
3223 + (((on & MTK_PHY_LED_ON_LINK10) ?
3224 + MTK_PHY_LED_BLINK_10TX : 0) |
3225 + ((on & MTK_PHY_LED_ON_LINK100) ?
3226 + MTK_PHY_LED_BLINK_100TX : 0) |
3227 + ((on & MTK_PHY_LED_ON_LINK1000) ?
3228 + MTK_PHY_LED_BLINK_1000TX : 0)) :
3229 + MTK_PHY_LED_BLINK_TX;
3230 + }
3231 +
3232 + if (blink || on)
3233 + set_bit(bit_netdev, &priv->led_state);
3234 + else
3235 + clear_bit(bit_netdev, &priv->led_state);
3236 +
3237 + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
3238 + MTK_PHY_LED1_ON_CTRL :
3239 + MTK_PHY_LED0_ON_CTRL,
3240 + MTK_PHY_LED_ON_FDX |
3241 + MTK_PHY_LED_ON_HDX |
3242 + MTK_PHY_LED_ON_LINK,
3243 + on);
3244 +
3245 + if (ret)
3246 + return ret;
3247 +
3248 + return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
3249 + MTK_PHY_LED1_BLINK_CTRL :
3250 + MTK_PHY_LED0_BLINK_CTRL, blink);
3251 +};
3252 +
3253 +static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
3254 +{
3255 + struct mtk_socphy_shared *priv = phydev->shared->priv;
3256 + u32 polarities;
3257 +
3258 + if (led_num == 0)
3259 + polarities = ~(priv->boottrap);
3260 + else
3261 + polarities = MTK_PHY_LED1_DEFAULT_POLARITIES;
3262 +
3263 + if (polarities & BIT(phydev->mdio.addr))
3264 + return true;
3265 +
3266 + return false;
3267 +}
3268 +
3269 +static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev)
3270 +{
3271 + struct pinctrl *pinctrl;
3272 + int index;
3273 +
3274 + /* Setup LED polarity according to bootstrap use of LED pins */
3275 + for (index = 0; index < 2; ++index)
3276 + phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
3277 + MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
3278 + MTK_PHY_LED_ON_POLARITY,
3279 + mt7988_phy_led_get_polarity(phydev, index) ?
3280 + MTK_PHY_LED_ON_POLARITY : 0);
3281 +
3282 + /* Only now setup pinctrl to avoid bogus blinking */
3283 + pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
3284 + if (IS_ERR(pinctrl))
3285 + dev_err(&phydev->mdio.bus->dev,
3286 + "Failed to setup PHY LED pinctrl\n");
3287 +
3288 + return 0;
3289 +}
3290 +
3291 +static int mt7988_phy_probe_shared(struct phy_device *phydev)
3292 +{
3293 + struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
3294 + struct mtk_socphy_shared *shared = phydev->shared->priv;
3295 + struct regmap *regmap;
3296 + u32 reg;
3297 + int ret;
3298 +
3299 + /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
3300 + * LED_C and LED_D respectively. At the same time those pins are used to
3301 + * bootstrap configuration of the reference clock source (LED_A),
3302 + * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
3303 + * In practice this is done using a LED and a resistor pulling the pin
3304 + * either to GND or to VIO.
3305 + * The detected value at boot time is accessible at run-time using the
3306 + * TPBANK0 register located in the gpio base of the pinctrl, in order
3307 + * to read it here it needs to be referenced by a phandle called
3308 + * 'mediatek,pio' in the MDIO bus hosting the PHY.
3309 + * The 4 bits in TPBANK0 are kept as package shared data and are used to
3310 + * set LED polarity for each of the LED0.
3311 + */
3312 + regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
3313 + if (IS_ERR(regmap))
3314 + return PTR_ERR(regmap);
3315 +
3316 + ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, &reg);
3317 + if (ret)
3318 + return ret;
3319 +
3320 + shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
3321 +
3322 + return 0;
3323 +}
3324 +
3325 +static void mt798x_phy_leds_state_init(struct phy_device *phydev)
3326 +{
3327 + int i;
3328 +
3329 + for (i = 0; i < 2; ++i)
3330 + mt798x_phy_led_hw_control_get(phydev, i, NULL);
3331 +}
3332 +
3333 +static int mt7988_phy_probe(struct phy_device *phydev)
3334 +{
3335 + struct mtk_socphy_shared *shared;
3336 + struct mtk_socphy_priv *priv;
3337 + int err;
3338 +
3339 + if (phydev->mdio.addr > 3)
3340 + return -EINVAL;
3341 +
3342 + err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
3343 + sizeof(struct mtk_socphy_shared));
3344 + if (err)
3345 + return err;
3346 +
3347 + if (phy_package_probe_once(phydev)) {
3348 + err = mt7988_phy_probe_shared(phydev);
3349 + if (err)
3350 + return err;
3351 + }
3352 +
3353 + shared = phydev->shared->priv;
3354 + priv = &shared->priv[phydev->mdio.addr];
3355 +
3356 + phydev->priv = priv;
3357 +
3358 + mt798x_phy_leds_state_init(phydev);
3359 +
3360 + err = mt7988_phy_fix_leds_polarities(phydev);
3361 + if (err)
3362 + return err;
3363 +
3364 + /* Disable TX power saving at probing to:
3365 + * 1. Meet common mode compliance test criteria
3366 + * 2. Make sure that TX-VCM calibration works fine
3367 + */
3368 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
3369 + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
3370 +
3371 + return mt798x_phy_calibration(phydev);
3372 +}
3373 +
3374 +static int mt7981_phy_probe(struct phy_device *phydev)
3375 +{
3376 + struct mtk_socphy_priv *priv;
3377 +
3378 + priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
3379 + GFP_KERNEL);
3380 + if (!priv)
3381 + return -ENOMEM;
3382 +
3383 + phydev->priv = priv;
3384 +
3385 + mt798x_phy_leds_state_init(phydev);
3386 +
3387 + return mt798x_phy_calibration(phydev);
3388 +}
3389 +
3390 +static struct phy_driver mtk_socphy_driver[] = {
3391 + {
3392 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
3393 + .name = "MediaTek MT7981 PHY",
3394 + .config_init = mt798x_phy_config_init,
3395 + .config_intr = genphy_no_config_intr,
3396 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3397 + .probe = mt7981_phy_probe,
3398 + .suspend = genphy_suspend,
3399 + .resume = genphy_resume,
3400 + .read_page = mtk_socphy_read_page,
3401 + .write_page = mtk_socphy_write_page,
3402 + .led_blink_set = mt798x_phy_led_blink_set,
3403 + .led_brightness_set = mt798x_phy_led_brightness_set,
3404 + .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
3405 + .led_hw_control_set = mt798x_phy_led_hw_control_set,
3406 + .led_hw_control_get = mt798x_phy_led_hw_control_get,
3407 + },
3408 + {
3409 + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
3410 + .name = "MediaTek MT7988 PHY",
3411 + .config_init = mt798x_phy_config_init,
3412 + .config_intr = genphy_no_config_intr,
3413 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3414 + .probe = mt7988_phy_probe,
3415 + .suspend = genphy_suspend,
3416 + .resume = genphy_resume,
3417 + .read_page = mtk_socphy_read_page,
3418 + .write_page = mtk_socphy_write_page,
3419 + .led_blink_set = mt798x_phy_led_blink_set,
3420 + .led_brightness_set = mt798x_phy_led_brightness_set,
3421 + .led_hw_is_supported = mt798x_phy_led_hw_is_supported,
3422 + .led_hw_control_set = mt798x_phy_led_hw_control_set,
3423 + .led_hw_control_get = mt798x_phy_led_hw_control_get,
3424 + },
3425 +};
3426 +
3427 +module_phy_driver(mtk_socphy_driver);
3428 +
3429 +static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = {
3430 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) },
3431 + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) },
3432 + { }
3433 +};
3434 +
3435 +MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
3436 +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
3437 +MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
3438 +MODULE_LICENSE("GPL");
3439 +
3440 +MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
3441 --- /dev/null
3442 +++ b/drivers/net/phy/mediatek/mtk-ge.c
3443 @@ -0,0 +1,114 @@
3444 +// SPDX-License-Identifier: GPL-2.0+
3445 +#include <linux/bitfield.h>
3446 +#include <linux/module.h>
3447 +#include <linux/phy.h>
3448 +
3449 +#define MTK_EXT_PAGE_ACCESS 0x1f
3450 +#define MTK_PHY_PAGE_STANDARD 0x0000
3451 +#define MTK_PHY_PAGE_EXTENDED 0x0001
3452 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002
3453 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
3454 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
3455 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
3456 +
3457 +static int mtk_gephy_read_page(struct phy_device *phydev)
3458 +{
3459 + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
3460 +}
3461 +
3462 +static int mtk_gephy_write_page(struct phy_device *phydev, int page)
3463 +{
3464 + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
3465 +}
3466 +
3467 +static void mtk_gephy_config_init(struct phy_device *phydev)
3468 +{
3469 + /* Disable EEE */
3470 + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
3471 +
3472 + /* Enable HW auto downshift */
3473 + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
3474 +
3475 + /* Increase SlvDPSready time */
3476 + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
3477 + __phy_write(phydev, 0x10, 0xafae);
3478 + __phy_write(phydev, 0x12, 0x2f);
3479 + __phy_write(phydev, 0x10, 0x8fae);
3480 + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
3481 +
3482 + /* Adjust 100_mse_threshold */
3483 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
3484 +
3485 + /* Disable mcc */
3486 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
3487 +}
3488 +
3489 +static int mt7530_phy_config_init(struct phy_device *phydev)
3490 +{
3491 + mtk_gephy_config_init(phydev);
3492 +
3493 + /* Increase post_update_timer */
3494 + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
3495 +
3496 + return 0;
3497 +}
3498 +
3499 +static int mt7531_phy_config_init(struct phy_device *phydev)
3500 +{
3501 + mtk_gephy_config_init(phydev);
3502 +
3503 + /* PHY link down power saving enable */
3504 + phy_set_bits(phydev, 0x17, BIT(4));
3505 + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
3506 +
3507 + /* Set TX Pair delay selection */
3508 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
3509 + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
3510 +
3511 + return 0;
3512 +}
3513 +
3514 +static struct phy_driver mtk_gephy_driver[] = {
3515 + {
3516 + PHY_ID_MATCH_EXACT(0x03a29412),
3517 + .name = "MediaTek MT7530 PHY",
3518 + .config_init = mt7530_phy_config_init,
3519 + /* Interrupts are handled by the switch, not the PHY
3520 + * itself.
3521 + */
3522 + .config_intr = genphy_no_config_intr,
3523 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3524 + .suspend = genphy_suspend,
3525 + .resume = genphy_resume,
3526 + .read_page = mtk_gephy_read_page,
3527 + .write_page = mtk_gephy_write_page,
3528 + },
3529 + {
3530 + PHY_ID_MATCH_EXACT(0x03a29441),
3531 + .name = "MediaTek MT7531 PHY",
3532 + .config_init = mt7531_phy_config_init,
3533 + /* Interrupts are handled by the switch, not the PHY
3534 + * itself.
3535 + */
3536 + .config_intr = genphy_no_config_intr,
3537 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3538 + .suspend = genphy_suspend,
3539 + .resume = genphy_resume,
3540 + .read_page = mtk_gephy_read_page,
3541 + .write_page = mtk_gephy_write_page,
3542 + },
3543 +};
3544 +
3545 +module_phy_driver(mtk_gephy_driver);
3546 +
3547 +static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
3548 + { PHY_ID_MATCH_EXACT(0x03a29441) },
3549 + { PHY_ID_MATCH_EXACT(0x03a29412) },
3550 + { }
3551 +};
3552 +
3553 +MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
3554 +MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
3555 +MODULE_LICENSE("GPL");
3556 +
3557 +MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);
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