git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 4df4f114c9a91d94e0e9356261e1b149146852ea Mon Sep 17 00:00:00 2001
   2 From: Sean Young <sean@mess.org>
   3 Date: Wed, 20 Dec 2023 14:24:25 +0000
   4 Subject: [PATCH 0941/1085] pwm: bcm2835: Allow PWM driver to be used in atomic
   5  context
   6
   7 commit fcc76072935935082efa127b97c7ddd880d2d793 upstream.
   8
   9 clk_get_rate() may do a mutex lock. Fetch the clock rate once, and prevent
  10 rate changes using clk_rate_exclusive_get().
  11
  12 Signed-off-by: Sean Young <sean@mess.org>
  13 Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
  14 Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
  15 ---
  16  drivers/pwm/pwm-bcm2835.c | 38 +++++++++++++++++++++++++++++---------
  17  1 file changed, 29 insertions(+), 9 deletions(-)
  18
  19 --- a/drivers/pwm/pwm-bcm2835.c
  20 +++ b/drivers/pwm/pwm-bcm2835.c
  21 @@ -28,6 +28,7 @@ struct bcm2835_pwm {
  22         struct device *dev;
  23         void __iomem *base;
  24         struct clk *clk;
  25 +       unsigned long rate;
  26  };
  27
  28  static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
  29 @@ -63,17 +64,11 @@ static int bcm2835_pwm_apply(struct pwm_
  30  {
  31
  32         struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
  33 -       unsigned long rate = clk_get_rate(pc->clk);
  34         unsigned long long period_cycles;
  35         u64 max_period;
  36
  37         u32 val;
  38
  39 -       if (!rate) {
  40 -               dev_err(pc->dev, "failed to get clock rate\n");
  41 -               return -EINVAL;
  42 -       }
  43 -
  44         /*
  45          * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
  46          * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
  47 @@ -88,13 +83,13 @@ static int bcm2835_pwm_apply(struct pwm_
  48          * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
  49          * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
  50          */
  51 -       max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, rate) - 1;
  52 +       max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, pc->rate) - 1;
  53
  54         if (state->period > max_period)
  55                 return -EINVAL;
  56
  57         /* set period */
  58 -       period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * rate, NSEC_PER_SEC);
  59 +       period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * pc->rate, NSEC_PER_SEC);
  60
  61         /* don't accept a period that is too small */
  62         if (period_cycles < PERIOD_MIN)
  63 @@ -103,7 +98,7 @@ static int bcm2835_pwm_apply(struct pwm_
  64         writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
  65
  66         /* set duty cycle */
  67 -       val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * rate, NSEC_PER_SEC);
  68 +       val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pc->rate, NSEC_PER_SEC);
  69         writel(val, pc->base + DUTY(pwm->hwpwm));
  70
  71         /* set polarity */
  72 @@ -132,6 +127,13 @@ static const struct pwm_ops bcm2835_pwm_
  73         .owner = THIS_MODULE,
  74  };
  75
  76 +static void devm_clk_rate_exclusive_put(void *data)
  77 +{
  78 +       struct clk *clk = data;
  79 +
  80 +       clk_rate_exclusive_put(clk);
  81 +}
  82 +
  83  static int bcm2835_pwm_probe(struct platform_device *pdev)
  84  {
  85         struct bcm2835_pwm *pc;
  86 @@ -152,8 +154,26 @@ static int bcm2835_pwm_probe(struct plat
  87                 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
  88                                      "clock not found\n");
  89
  90 +       ret = clk_rate_exclusive_get(pc->clk);
  91 +       if (ret)
  92 +               return dev_err_probe(&pdev->dev, ret,
  93 +                                    "fail to get exclusive rate\n");
  94 +
  95 +       ret = devm_add_action_or_reset(&pdev->dev, devm_clk_rate_exclusive_put,
  96 +                                      pc->clk);
  97 +       if (ret) {
  98 +               clk_rate_exclusive_put(pc->clk);
  99 +               return ret;
 100 +       }
 101 +
 102 +       pc->rate = clk_get_rate(pc->clk);
 103 +       if (!pc->rate)
 104 +               return dev_err_probe(&pdev->dev, -EINVAL,
 105 +                                    "failed to get clock rate\n");
 106 +
 107         pc->chip.dev = &pdev->dev;
 108         pc->chip.ops = &bcm2835_pwm_ops;
 109 +       pc->chip.atomic = true;
 110         pc->chip.npwm = 2;
 111
 112         ret = devm_pwmchip_add(&pdev->dev, &pc->chip);