git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From: Gabor Juhos <j4g8y7@gmail.com>
   2 Date: Fri, 02 May 2025 21:31:16 +0200
   3 Subject: [PATCH next 1/2] mtd: nand: qpic-common: add defines for ECC_MODE
   4  values
   5
   6 Add defines for the values of the ECC_MODE field of the NAND_DEV0_ECC_CFG
   7 register and change both the 'qcom-nandc' and 'spi-qpic-snand' drivers to
   8 use those instead of magic numbers.
   9
  10 No functional changes. This is in preparation for adding 8 bit ECC strength
  11 support for the 'spi-qpic-snand' driver.
  12
  13 Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
  14 ---
  15  drivers/mtd/nand/raw/qcom_nandc.c    | 6 +++---
  16  drivers/spi/spi-qpic-snand.c         | 2 +-
  17  include/linux/mtd/nand-qpic-common.h | 2 ++
  18  3 files changed, 6 insertions(+), 4 deletions(-)
  19
  20 --- a/drivers/mtd/nand/raw/qcom_nandc.c
  21 +++ b/drivers/mtd/nand/raw/qcom_nandc.c
  22 @@ -1379,7 +1379,7 @@ static int qcom_nand_attach_chip(struct
  23         struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  24         int cwperpage, bad_block_byte, ret;
  25         bool wide_bus;
  26 -       int ecc_mode = 1;
  27 +       int ecc_mode = ECC_MODE_8BIT;
  28
  29         /* controller only supports 512 bytes data steps */
  30         ecc->size = NANDC_STEP_SIZE;
  31 @@ -1400,7 +1400,7 @@ static int qcom_nand_attach_chip(struct
  32         if (ecc->strength >= 8) {
  33                 /* 8 bit ECC defaults to BCH ECC on all platforms */
  34                 host->bch_enabled = true;
  35 -               ecc_mode = 1;
  36 +               ecc_mode = ECC_MODE_8BIT;
  37
  38                 if (wide_bus) {
  39                         host->ecc_bytes_hw = 14;
  40 @@ -1420,7 +1420,7 @@ static int qcom_nand_attach_chip(struct
  41                 if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
  42                         /* BCH */
  43                         host->bch_enabled = true;
  44 -                       ecc_mode = 0;
  45 +                       ecc_mode = ECC_MODE_4BIT;
  46
  47                         if (wide_bus) {
  48                                 host->ecc_bytes_hw = 8;
  49 --- a/drivers/spi/spi-qpic-snand.c
  50 +++ b/drivers/spi/spi-qpic-snand.c
  51 @@ -349,7 +349,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
  52                                FIELD_PREP(ECC_SW_RESET, 0) |
  53                                FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
  54                                FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
  55 -                              FIELD_PREP(ECC_MODE_MASK, 0) |
  56 +                              FIELD_PREP(ECC_MODE_MASK, ECC_MODE_4BIT) |
  57                                FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
  58
  59         ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
  60 --- a/include/linux/mtd/nand-qpic-common.h
  61 +++ b/include/linux/mtd/nand-qpic-common.h
  62 @@ -101,6 +101,8 @@
  63  #define        ECC_SW_RESET                    BIT(1)
  64  #define        ECC_MODE                        4
  65  #define        ECC_MODE_MASK                   GENMASK(5, 4)
  66 +#define        ECC_MODE_4BIT                   0
  67 +#define        ECC_MODE_8BIT                   1
  68  #define        ECC_PARITY_SIZE_BYTES_BCH       8
  69  #define        ECC_PARITY_SIZE_BYTES_BCH_MASK  GENMASK(12, 8)
  70  #define        ECC_NUM_DATA_BYTES              16