git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From dcf4fef6631c302f9bdd188979fe3172e47a29c7 Mon Sep 17 00:00:00 2001
   2 From: Aurelien Jarno <aurelien@aurel32.net>
   3 Date: Tue, 30 Jul 2024 17:11:04 +0100
   4 Subject: [PATCH] hwrng: rockchip - add hwrng driver for Rockchip RK3568 SoC
   5
   6 Rockchip SoCs used to have a random number generator as part of their
   7 crypto device, and support for it has to be added to the corresponding
   8 driver. However newer Rockchip SoCs like the RK3568 have an independent
   9 True Random Number Generator device. This patch adds a driver for it,
  10 greatly inspired from the downstream driver.
  11
  12 The TRNG device does not seem to have a signal conditionner and the FIPS
  13 140-2 test returns a lot of failures. They can be reduced by increasing
  14 RK_RNG_SAMPLE_CNT, in a tradeoff between quality and speed. This value
  15 has been adjusted to get ~90% of successes and the quality value has
  16 been set accordingly.
  17
  18 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  19 [daniel@makrotpia.org: code style fixes]
  20 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  21 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  22 Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
  23 ---
  24  MAINTAINERS                           |   1 +
  25  drivers/char/hw_random/Kconfig        |  14 ++
  26  drivers/char/hw_random/Makefile       |   1 +
  27  drivers/char/hw_random/rockchip-rng.c | 227 ++++++++++++++++++++++++++
  28  4 files changed, 243 insertions(+)
  29  create mode 100644 drivers/char/hw_random/rockchip-rng.c
  30
  31 --- a/drivers/char/hw_random/Kconfig
  32 +++ b/drivers/char/hw_random/Kconfig
  33 @@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
  34           To compile this driver as a module, choose M here.
  35           The module will be called jh7110-trng.
  36
  37 +config HW_RANDOM_ROCKCHIP
  38 +       tristate "Rockchip True Random Number Generator"
  39 +       depends on HW_RANDOM && (ARCH_ROCKCHIP || COMPILE_TEST)
  40 +       depends on HAS_IOMEM
  41 +       default HW_RANDOM
  42 +       help
  43 +         This driver provides kernel-side support for the True Random Number
  44 +         Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
  45 +
  46 +         To compile this driver as a module, choose M here: the
  47 +         module will be called rockchip-rng.
  48 +
  49 +         If unsure, say Y.
  50 +
  51  endif # HW_RANDOM
  52
  53  config UML_RANDOM
  54 --- a/drivers/char/hw_random/Makefile
  55 +++ b/drivers/char/hw_random/Makefile
  56 @@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
  57  obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
  58  obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
  59  obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
  60 +obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
  61  obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
  62 --- /dev/null
  63 +++ b/drivers/char/hw_random/rockchip-rng.c
  64 @@ -0,0 +1,227 @@
  65 +// SPDX-License-Identifier: GPL-2.0
  66 +/*
  67 + * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
  68 + *
  69 + * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
  70 + * Copyright (c) 2022, Aurelien Jarno
  71 + * Authors:
  72 + *  Lin Jinhan <troy.lin@rock-chips.com>
  73 + *  Aurelien Jarno <aurelien@aurel32.net>
  74 + */
  75 +#include <linux/clk.h>
  76 +#include <linux/hw_random.h>
  77 +#include <linux/io.h>
  78 +#include <linux/iopoll.h>
  79 +#include <linux/kernel.h>
  80 +#include <linux/module.h>
  81 +#include <linux/of.h>
  82 +#include <linux/platform_device.h>
  83 +#include <linux/pm_runtime.h>
  84 +#include <linux/reset.h>
  85 +#include <linux/slab.h>
  86 +
  87 +#define RK_RNG_AUTOSUSPEND_DELAY       100
  88 +#define RK_RNG_MAX_BYTE                        32
  89 +#define RK_RNG_POLL_PERIOD_US          100
  90 +#define RK_RNG_POLL_TIMEOUT_US         10000
  91 +
  92 +/*
  93 + * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is
  94 + * a tradeoff between speed and quality and has been adjusted to get a quality
  95 + * of ~900 (~87.5% of FIPS 140-2 successes).
  96 + */
  97 +#define RK_RNG_SAMPLE_CNT              1000
  98 +
  99 +/* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
 100 +#define TRNG_RST_CTL                   0x0004
 101 +#define TRNG_RNG_CTL                   0x0400
 102 +#define TRNG_RNG_CTL_LEN_64_BIT                (0x00 << 4)
 103 +#define TRNG_RNG_CTL_LEN_128_BIT       (0x01 << 4)
 104 +#define TRNG_RNG_CTL_LEN_192_BIT       (0x02 << 4)
 105 +#define TRNG_RNG_CTL_LEN_256_BIT       (0x03 << 4)
 106 +#define TRNG_RNG_CTL_OSC_RING_SPEED_0  (0x00 << 2)
 107 +#define TRNG_RNG_CTL_OSC_RING_SPEED_1  (0x01 << 2)
 108 +#define TRNG_RNG_CTL_OSC_RING_SPEED_2  (0x02 << 2)
 109 +#define TRNG_RNG_CTL_OSC_RING_SPEED_3  (0x03 << 2)
 110 +#define TRNG_RNG_CTL_MASK              GENMASK(15, 0)
 111 +#define TRNG_RNG_CTL_ENABLE            BIT(1)
 112 +#define TRNG_RNG_CTL_START             BIT(0)
 113 +#define TRNG_RNG_SAMPLE_CNT            0x0404
 114 +#define TRNG_RNG_DOUT                  0x0410
 115 +
 116 +struct rk_rng {
 117 +       struct hwrng rng;
 118 +       void __iomem *base;
 119 +       struct reset_control *rst;
 120 +       int clk_num;
 121 +       struct clk_bulk_data *clk_bulks;
 122 +};
 123 +
 124 +/* The mask in the upper 16 bits determines the bits that are updated */
 125 +static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
 126 +{
 127 +       writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
 128 +}
 129 +
 130 +static int rk_rng_init(struct hwrng *rng)
 131 +{
 132 +       struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 133 +       int ret;
 134 +
 135 +       /* start clocks */
 136 +       ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
 137 +       if (ret < 0) {
 138 +               dev_err((struct device *) rk_rng->rng.priv,
 139 +                       "Failed to enable clks %d\n", ret);
 140 +               return ret;
 141 +       }
 142 +
 143 +       /* set the sample period */
 144 +       writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
 145 +
 146 +       /* set osc ring speed and enable it */
 147 +       rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_LEN_256_BIT |
 148 +                                TRNG_RNG_CTL_OSC_RING_SPEED_0 |
 149 +                                TRNG_RNG_CTL_ENABLE,
 150 +                        TRNG_RNG_CTL_MASK);
 151 +
 152 +       return 0;
 153 +}
 154 +
 155 +static void rk_rng_cleanup(struct hwrng *rng)
 156 +{
 157 +       struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 158 +
 159 +       /* stop TRNG */
 160 +       rk_rng_write_ctl(rk_rng, 0, TRNG_RNG_CTL_MASK);
 161 +
 162 +       /* stop clocks */
 163 +       clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
 164 +}
 165 +
 166 +static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
 167 +{
 168 +       struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
 169 +       size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
 170 +       u32 reg;
 171 +       int ret = 0;
 172 +
 173 +       ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv);
 174 +       if (ret < 0)
 175 +               return ret;
 176 +
 177 +       /* Start collecting random data */
 178 +       rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_START, TRNG_RNG_CTL_START);
 179 +
 180 +       ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg,
 181 +                                !(reg & TRNG_RNG_CTL_START),
 182 +                                RK_RNG_POLL_PERIOD_US,
 183 +                                RK_RNG_POLL_TIMEOUT_US);
 184 +       if (ret < 0)
 185 +               goto out;
 186 +
 187 +       /* Read random data stored in the registers */
 188 +       memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read);
 189 +out:
 190 +       pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
 191 +       pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
 192 +
 193 +       return (ret < 0) ? ret : to_read;
 194 +}
 195 +
 196 +static int rk_rng_probe(struct platform_device *pdev)
 197 +{
 198 +       struct device *dev = &pdev->dev;
 199 +       struct rk_rng *rk_rng;
 200 +       int ret;
 201 +
 202 +       rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL);
 203 +       if (!rk_rng)
 204 +               return -ENOMEM;
 205 +
 206 +       rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
 207 +       if (IS_ERR(rk_rng->base))
 208 +               return PTR_ERR(rk_rng->base);
 209 +
 210 +       rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks);
 211 +       if (rk_rng->clk_num < 0)
 212 +               return dev_err_probe(dev, rk_rng->clk_num,
 213 +                                    "Failed to get clks property\n");
 214 +
 215 +       rk_rng->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
 216 +       if (IS_ERR(rk_rng->rst))
 217 +               return dev_err_probe(dev, PTR_ERR(rk_rng->rst),
 218 +                                    "Failed to get reset property\n");
 219 +
 220 +       reset_control_assert(rk_rng->rst);
 221 +       udelay(2);
 222 +       reset_control_deassert(rk_rng->rst);
 223 +
 224 +       platform_set_drvdata(pdev, rk_rng);
 225 +
 226 +       rk_rng->rng.name = dev_driver_string(dev);
 227 +       if (!IS_ENABLED(CONFIG_PM)) {
 228 +               rk_rng->rng.init = rk_rng_init;
 229 +               rk_rng->rng.cleanup = rk_rng_cleanup;
 230 +       }
 231 +       rk_rng->rng.read = rk_rng_read;
 232 +       rk_rng->rng.priv = (unsigned long) dev;
 233 +       rk_rng->rng.quality = 900;
 234 +
 235 +       pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
 236 +       pm_runtime_use_autosuspend(dev);
 237 +       devm_pm_runtime_enable(dev);
 238 +
 239 +       ret = devm_hwrng_register(dev, &rk_rng->rng);
 240 +       if (ret)
 241 +               return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
 242 +
 243 +       return 0;
 244 +}
 245 +
 246 +static int __maybe_unused rk_rng_runtime_suspend(struct device *dev)
 247 +{
 248 +       struct rk_rng *rk_rng = dev_get_drvdata(dev);
 249 +
 250 +       rk_rng_cleanup(&rk_rng->rng);
 251 +
 252 +       return 0;
 253 +}
 254 +
 255 +static int __maybe_unused rk_rng_runtime_resume(struct device *dev)
 256 +{
 257 +       struct rk_rng *rk_rng = dev_get_drvdata(dev);
 258 +
 259 +       return rk_rng_init(&rk_rng->rng);
 260 +}
 261 +
 262 +static const struct dev_pm_ops rk_rng_pm_ops = {
 263 +       SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
 264 +                               rk_rng_runtime_resume, NULL)
 265 +       SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 266 +                               pm_runtime_force_resume)
 267 +};
 268 +
 269 +static const struct of_device_id rk_rng_dt_match[] = {
 270 +       { .compatible = "rockchip,rk3568-rng", },
 271 +       { /* sentinel */ },
 272 +};
 273 +
 274 +MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
 275 +
 276 +static struct platform_driver rk_rng_driver = {
 277 +       .driver = {
 278 +               .name   = "rockchip-rng",
 279 +               .pm     = &rk_rng_pm_ops,
 280 +               .of_match_table = rk_rng_dt_match,
 281 +       },
 282 +       .probe  = rk_rng_probe,
 283 +};
 284 +
 285 +module_platform_driver(rk_rng_driver);
 286 +
 287 +MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver");
 288 +MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
 289 +MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
 290 +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
 291 +MODULE_LICENSE("GPL");