git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From: Varadarajan Narayanan <quic_varada@quicinc.com>
   2 Date: Thu, 2 Jan 2025 17:00:15 +0530
   3 Subject: [PATCH] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
   4
   5 From: Nitheesh Sekar <quic_nsekar@quicinc.com>
   6
   7 Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
   8
   9 Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
  10 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
  11 ---
  12 --- /dev/null
  13 +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
  14 @@ -0,0 +1,71 @@
  15 +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  16 +%YAML 1.2
  17 +---
  18 +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
  19 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  20 +
  21 +title: Qualcomm UNIPHY PCIe 28LP PHY
  22 +
  23 +maintainers:
  24 +  - Nitheesh Sekar <quic_nsekar@quicinc.com>
  25 +  - Varadarajan Narayanan <quic_varada@quicinc.com>
  26 +
  27 +description:
  28 +  PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
  29 +
  30 +properties:
  31 +  compatible:
  32 +    enum:
  33 +      - qcom,ipq5332-uniphy-pcie-phy
  34 +
  35 +  reg:
  36 +    maxItems: 1
  37 +
  38 +  clocks:
  39 +    items:
  40 +      - description: pcie pipe clock
  41 +      - description: pcie ahb clock
  42 +
  43 +  resets:
  44 +    items:
  45 +      - description: phy reset
  46 +      - description: ahb reset
  47 +      - description: cfg reset
  48 +
  49 +  "#phy-cells":
  50 +    const: 0
  51 +
  52 +  "#clock-cells":
  53 +    const: 0
  54 +
  55 +  num-lanes: true
  56 +
  57 +required:
  58 +  - compatible
  59 +  - reg
  60 +  - clocks
  61 +  - resets
  62 +  - "#phy-cells"
  63 +  - "#clock-cells"
  64 +
  65 +additionalProperties: false
  66 +
  67 +examples:
  68 +  - |
  69 +    #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
  70 +
  71 +    pcie0_phy: phy@4b0000 {
  72 +        compatible = "qcom,ipq5332-uniphy-pcie-phy";
  73 +        reg = <0x004b0000 0x800>;
  74 +
  75 +        clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
  76 +                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
  77 +
  78 +        resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
  79 +                 <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
  80 +                 <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
  81 +
  82 +        #clock-cells = <0>;
  83 +
  84 +        #phy-cells = <0>;
  85 +    };