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1 From f87a17ed3b51fba4dfdd8f8b643b5423a85fc551 Mon Sep 17 00:00:00 2001
2 From: Heiner Kallweit <hkallweit1@gmail.com>
3 Date: Tue, 15 Oct 2024 07:47:14 +0200
4 Subject: [PATCH] net: phy: realtek: merge the drivers for internal NBase-T
5 PHY's
6
7 The Realtek RTL8125/RTL8126 NBase-T MAC/PHY chips have internal PHY's
8 which are register-compatible, at least for the registers we use here.
9 So let's use just one PHY driver to support all of them.
10 These internal PHY's exist also as external C45 PHY's, but on the
11 internal PHY's no access to MMD registers is possible. This can be
12 used to differentiate between the internal and external version.
13
14 As a side effect the drivers for two now external-only drivers don't
15 require read_mmd/write_mmd hooks any longer.
16
17 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
18 Link: https://patch.msgid.link/c57081a6-811f-4571-ab35-34f4ca6de9af@gmail.com
19 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
20 ---
21 drivers/net/phy/realtek.c | 53 +++++++++++++++++++++++++++++++--------
22 1 file changed, 43 insertions(+), 10 deletions(-)
23
24 --- a/drivers/net/phy/realtek.c
25 +++ b/drivers/net/phy/realtek.c
26 @@ -95,6 +95,7 @@
27
28 #define RTL_GENERIC_PHYID 0x001cc800
29 #define RTL_8211FVD_PHYID 0x001cc878
30 +#define RTL_8221B 0x001cc840
31 #define RTL_8221B_VB_CG 0x001cc849
32 #define RTL_8221B_VN_CG 0x001cc84a
33 #define RTL_8251B 0x001cc862
34 @@ -1077,6 +1078,23 @@ static bool rtlgen_supports_2_5gbps(stru
35 return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
36 }
37
38 +/* On internal PHY's MMD reads over C22 always return 0.
39 + * Check a MMD register which is known to be non-zero.
40 + */
41 +static bool rtlgen_supports_mmd(struct phy_device *phydev)
42 +{
43 + int val;
44 +
45 + phy_lock_mdio_bus(phydev);
46 + __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
47 + __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
48 + __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
49 + val = __phy_read(phydev, MII_MMD_DATA);
50 + phy_unlock_mdio_bus(phydev);
51 +
52 + return val > 0;
53 +}
54 +
55 static int rtlgen_match_phy_device(struct phy_device *phydev)
56 {
57 return phydev->phy_id == RTL_GENERIC_PHYID &&
58 @@ -1086,7 +1104,8 @@ static int rtlgen_match_phy_device(struc
59 static int rtl8226_match_phy_device(struct phy_device *phydev)
60 {
61 return phydev->phy_id == RTL_GENERIC_PHYID &&
62 - rtlgen_supports_2_5gbps(phydev);
63 + rtlgen_supports_2_5gbps(phydev) &&
64 + rtlgen_supports_mmd(phydev);
65 }
66
67 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
68 @@ -1098,6 +1117,11 @@ static int rtlgen_is_c45_match(struct ph
69 return !is_c45 && (id == phydev->phy_id);
70 }
71
72 +static int rtl8221b_match_phy_device(struct phy_device *phydev)
73 +{
74 + return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
75 +}
76 +
77 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
78 {
79 return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
80 @@ -1118,9 +1142,21 @@ static int rtl8221b_vn_cg_c45_match_phy_
81 return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
82 }
83
84 -static int rtl8251b_c22_match_phy_device(struct phy_device *phydev)
85 +static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
86 {
87 - return rtlgen_is_c45_match(phydev, RTL_8251B, false);
88 + if (phydev->is_c45)
89 + return false;
90 +
91 + switch (phydev->phy_id) {
92 + case RTL_GENERIC_PHYID:
93 + case RTL_8221B:
94 + case RTL_8251B:
95 + break;
96 + default:
97 + return false;
98 + }
99 +
100 + return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
101 }
102
103 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
104 @@ -1382,10 +1418,8 @@ static struct phy_driver realtek_drvs[]
105 .resume = rtlgen_resume,
106 .read_page = rtl821x_read_page,
107 .write_page = rtl821x_write_page,
108 - .read_mmd = rtl822x_read_mmd,
109 - .write_mmd = rtl822x_write_mmd,
110 }, {
111 - PHY_ID_MATCH_EXACT(0x001cc840),
112 + .match_phy_device = rtl8221b_match_phy_device,
113 .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
114 .get_features = rtl822x_get_features,
115 .config_aneg = rtl822x_config_aneg,
116 @@ -1396,8 +1430,6 @@ static struct phy_driver realtek_drvs[]
117 .resume = rtlgen_resume,
118 .read_page = rtl821x_read_page,
119 .write_page = rtl821x_write_page,
120 - .read_mmd = rtl822x_read_mmd,
121 - .write_mmd = rtl822x_write_mmd,
122 }, {
123 PHY_ID_MATCH_EXACT(0x001cc838),
124 .name = "RTL8226-CG 2.5Gbps PHY",
125 @@ -1475,8 +1507,9 @@ static struct phy_driver realtek_drvs[]
126 .read_page = rtl821x_read_page,
127 .write_page = rtl821x_write_page,
128 }, {
129 - .match_phy_device = rtl8251b_c22_match_phy_device,
130 - .name = "RTL8126A-internal 5Gbps PHY",
131 + .match_phy_device = rtl_internal_nbaset_match_phy_device,
132 + .name = "Realtek Internal NBASE-T PHY",
133 + .flags = PHY_IS_INTERNAL,
134 .get_features = rtl822x_get_features,
135 .config_aneg = rtl822x_config_aneg,
136 .read_status = rtl822x_read_status,
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