git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
   2 From: Damon Ding <damon.ding@rock-chips.com>
   3 Date: Thu, 6 Feb 2025 11:03:30 +0800
   4 Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
   5
   6 The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
   7 and eDP Link. Therefore, it is better to name it hdptxphy0 other than
   8 hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
   9
  10 Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
  11 Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
  12 [added armsom-sige7, where hdmi-support was added recently and also
  13  the hdptxphy0-as-dclk source I just added]
  14 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  15
  16 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  17 +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  18 @@ -1262,7 +1262,7 @@
  19                          <&cru DCLK_VOP2>,
  20                          <&cru DCLK_VOP3>,
  21                          <&cru PCLK_VOP_ROOT>,
  22 -                        <&hdptxphy_hdmi0>;
  23 +                        <&hdptxphy0>;
  24                 clock-names = "aclk",
  25                               "hclk",
  26                               "dclk_vp0",
  27 @@ -1387,7 +1387,7 @@
  28                              <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
  29                              <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
  30                 interrupt-names = "avp", "cec", "earc", "main", "hpd";
  31 -               phys = <&hdptxphy_hdmi0>;
  32 +               phys = <&hdptxphy0>;
  33                 pinctrl-names = "default";
  34                 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
  35                              &hdmim0_tx0_scl &hdmim0_tx0_sda>;
  36 @@ -2810,7 +2810,7 @@
  37                 #dma-cells = <1>;
  38         };
  39
  40 -       hdptxphy_hdmi0: phy@fed60000 {
  41 +       hdptxphy0: phy@fed60000 {
  42                 compatible = "rockchip,rk3588-hdptx-phy";
  43                 reg = <0x0 0xfed60000 0x0 0x2000>;
  44                 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;