git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 3d21dabd055ca064880e775892a10c5e69fdf5e9 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Tue, 13 Aug 2024 17:18:51 +0100
   4 Subject: [PATCH 1227/1350] drm/vc4: Also power down the PLL core when
   5  resetting PHY
   6
   7 The current reset code doesn't actually stop the hdmi output.
   8 That makes it difficult for displays to handle a mode set.
   9
  10 Powering down the PLL does actually remove the hdmi signal
  11 and makes mode sets more reliable
  12
  13 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  14 ---
  15  drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 2 ++
  16  1 file changed, 2 insertions(+)
  17
  18 --- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
  19 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
  20 @@ -137,6 +137,7 @@
  21  #define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS     BIT(13)
  22  #define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK         VC4_MASK(9, 0)
  23
  24 +#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN                BIT(4)
  25  #define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK    VC4_MASK(3, 2)
  26  #define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK                VC4_MASK(1, 0)
  27
  28 @@ -947,6 +948,7 @@ static void vc6_hdmi_reset_phy(struct vc
  29
  30         HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);
  31         HDMI_WRITE(HDMI_TX_PHY_POWERUP_CTL, 0);
  32 +       HDMI_WRITE(HDMI_TX_PHY_PLL_POST_KDIV, VC6_HDMI_TX_PHY_PLL_POST_KDIV_BYPASS_EN);
  33  }
  34
  35  void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,