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   1 From 249b78298078448a699c39356d27d8183af4b281 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Tue, 25 Feb 2025 09:04:07 +0100
   4 Subject: [PATCH] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581
   5  SoC
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Configure PBus base address and address mask to allow the hw
  11 to detect if a given address is accessible on PCIe controller.
  12
  13 Fixes: f6ab898356dd ("PCI: mediatek-gen3: Add Airoha EN7581 support")
  14 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  15 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  16 Link: https://lore.kernel.org/r/20250225-en7581-pcie-pbus-csr-v4-2-24324382424a@kernel.org
  17 Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
  18 ---
  19  drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++++-
  20  1 file changed, 27 insertions(+), 1 deletion(-)
  21
  22 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
  23 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
  24 @@ -15,6 +15,7 @@
  25  #include <linux/irqchip/chained_irq.h>
  26  #include <linux/irqdomain.h>
  27  #include <linux/kernel.h>
  28 +#include <linux/mfd/syscon.h>
  29  #include <linux/module.h>
  30  #include <linux/msi.h>
  31  #include <linux/of_device.h>
  32 @@ -24,6 +25,7 @@
  33  #include <linux/platform_device.h>
  34  #include <linux/pm_domain.h>
  35  #include <linux/pm_runtime.h>
  36 +#include <linux/regmap.h>
  37  #include <linux/reset.h>
  38
  39  #include "../pci.h"
  40 @@ -892,9 +894,13 @@ static int mtk_pcie_parse_port(struct mt
  41
  42  static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
  43  {
  44 +       struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
  45         struct device *dev = pcie->dev;
  46 +       struct resource_entry *entry;
  47 +       struct regmap *pbus_regmap;
  48 +       u32 val, args[2], size;
  49 +       resource_size_t addr;
  50         int err;
  51 -       u32 val;
  52
  53         /*
  54          * The controller may have been left out of reset by the bootloader
  55 @@ -907,6 +913,26 @@ static int mtk_pcie_en7581_power_up(stru
  56         msleep(PCIE_EN7581_RESET_TIME_MS);
  57
  58         /*
  59 +        * Configure PBus base address and base address mask to allow the
  60 +        * hw to detect if a given address is accessible on PCIe controller.
  61 +        */
  62 +       pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
  63 +                                                          "mediatek,pbus-csr",
  64 +                                                          ARRAY_SIZE(args),
  65 +                                                          args);
  66 +       if (IS_ERR(pbus_regmap))
  67 +               return PTR_ERR(pbus_regmap);
  68 +
  69 +       entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
  70 +       if (!entry)
  71 +               return -ENODEV;
  72 +
  73 +       addr = entry->res->start - entry->offset;
  74 +       regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
  75 +       size = lower_32_bits(resource_size(entry->res));
  76 +       regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
  77 +
  78 +       /*
  79          * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
  80          * requires PHY initialization and power-on before PHY reset deassert.
  81          */