git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001
   2 From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
   3 Date: Wed, 11 Dec 2024 01:06:15 +0200
   4 Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
   5
   6 In preparation to enable the second HDMI output port found on RK3588
   7 SoC, add the related PHY node.  This requires a GRF, hence add the
   8 dependent node as well.
   9
  10 Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
  11 Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
  12 Tested-by: Alexandre ARNOUD <aarnoud@me.com>
  13 Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
  14 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  15
  16 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
  17 +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
  18 @@ -67,6 +67,11 @@
  19                 };
  20         };
  21
  22 +       hdptxphy1_grf: syscon@fd5e4000 {
  23 +               compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
  24 +               reg = <0x0 0xfd5e4000 0x0 0x100>;
  25 +       };
  26 +
  27         i2s8_8ch: i2s@fddc8000 {
  28                 compatible = "rockchip,rk3588-i2s-tdm";
  29                 reg = <0x0 0xfddc8000 0x0 0x1000>;
  30 @@ -395,6 +400,22 @@
  31                 };
  32         };
  33
  34 +       hdptxphy1: phy@fed70000 {
  35 +               compatible = "rockchip,rk3588-hdptx-phy";
  36 +               reg = <0x0 0xfed70000 0x0 0x2000>;
  37 +               clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
  38 +               clock-names = "ref", "apb";
  39 +               #phy-cells = <0>;
  40 +               resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
  41 +                        <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
  42 +                        <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
  43 +                        <&cru SRST_HDPTX1_LCPLL>;
  44 +               reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
  45 +                             "lcpll";
  46 +               rockchip,grf = <&hdptxphy1_grf>;
  47 +               status = "disabled";
  48 +       };
  49 +
  50         usbdp_phy1: phy@fed90000 {
  51                 compatible = "rockchip,rk3588-usbdp-phy";
  52                 reg = <0x0 0xfed90000 0x0 0x10000>;