git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From ee9eabbe3f0f0c7458d89840add97e54d4e0bccf Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Wed, 3 Jul 2024 18:12:43 +0200
   4 Subject: [PATCH 2/3] PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset
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   9
  10 Use reset_bulk APIs to manage PHY reset lines.
  11
  12 This is a preliminary patch in order to add Airoha EN7581 PCIe support.
  13
  14 Link: https://lore.kernel.org/linux-pci/3ceb83bc0defbcf868521f8df4b9100e55ec2614.1720022580.git.lorenzo@kernel.org
  15 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  16 Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
  17 Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
  18 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  19 Acked-by: Jianjun Wang <jianjun.wang@mediatek.com>
  20 ---
  21  drivers/pci/controller/pcie-mediatek-gen3.c | 45 +++++++++++++++------
  22  1 file changed, 33 insertions(+), 12 deletions(-)
  23
  24 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
  25 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
  26 @@ -100,14 +100,21 @@
  27  #define PCIE_ATR_TLP_TYPE_MEM          PCIE_ATR_TLP_TYPE(0)
  28  #define PCIE_ATR_TLP_TYPE_IO           PCIE_ATR_TLP_TYPE(2)
  29
  30 +#define MAX_NUM_PHY_RESETS             1
  31 +
  32  struct mtk_gen3_pcie;
  33
  34  /**
  35   * struct mtk_gen3_pcie_pdata - differentiate between host generations
  36   * @power_up: pcie power_up callback
  37 + * @phy_resets: phy reset lines SoC data.
  38   */
  39  struct mtk_gen3_pcie_pdata {
  40         int (*power_up)(struct mtk_gen3_pcie *pcie);
  41 +       struct {
  42 +               const char *id[MAX_NUM_PHY_RESETS];
  43 +               int num_resets;
  44 +       } phy_resets;
  45  };
  46
  47  /**
  48 @@ -128,7 +135,7 @@ struct mtk_msi_set {
  49   * @base: IO mapped register base
  50   * @reg_base: physical register base
  51   * @mac_reset: MAC reset control
  52 - * @phy_reset: PHY reset control
  53 + * @phy_resets: PHY reset controllers
  54   * @phy: PHY controller block
  55   * @clks: PCIe clocks
  56   * @num_clks: PCIe clocks count for this port
  57 @@ -148,7 +155,7 @@ struct mtk_gen3_pcie {
  58         void __iomem *base;
  59         phys_addr_t reg_base;
  60         struct reset_control *mac_reset;
  61 -       struct reset_control *phy_reset;
  62 +       struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS];
  63         struct phy *phy;
  64         struct clk_bulk_data *clks;
  65         int num_clks;
  66 @@ -788,10 +795,10 @@ static int mtk_pcie_setup_irq(struct mtk
  67
  68  static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
  69  {
  70 +       int i, ret, num_resets = pcie->soc->phy_resets.num_resets;
  71         struct device *dev = pcie->dev;
  72         struct platform_device *pdev = to_platform_device(dev);
  73         struct resource *regs;
  74 -       int ret;
  75
  76         regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
  77         if (!regs)
  78 @@ -804,12 +811,12 @@ static int mtk_pcie_parse_port(struct mt
  79
  80         pcie->reg_base = regs->start;
  81
  82 -       pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
  83 -       if (IS_ERR(pcie->phy_reset)) {
  84 -               ret = PTR_ERR(pcie->phy_reset);
  85 -               if (ret != -EPROBE_DEFER)
  86 -                       dev_err(dev, "failed to get PHY reset\n");
  87 +       for (i = 0; i < num_resets; i++)
  88 +               pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
  89
  90 +       ret = devm_reset_control_bulk_get_optional_shared(dev, num_resets, pcie->phy_resets);
  91 +       if (ret) {
  92 +               dev_err(dev, "failed to get PHY bulk reset\n");
  93                 return ret;
  94         }
  95
  96 @@ -846,7 +853,11 @@ static int mtk_pcie_power_up(struct mtk_
  97         int err;
  98
  99         /* PHY power on and enable pipe clock */
 100 -       reset_control_deassert(pcie->phy_reset);
 101 +       err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 102 +       if (err) {
 103 +               dev_err(dev, "failed to deassert PHYs\n");
 104 +               return err;
 105 +       }
 106
 107         err = phy_init(pcie->phy);
 108         if (err) {
 109 @@ -882,7 +893,7 @@ err_clk_init:
 110  err_phy_on:
 111         phy_exit(pcie->phy);
 112  err_phy_init:
 113 -       reset_control_assert(pcie->phy_reset);
 114 +       reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 115
 116         return err;
 117  }
 118 @@ -897,7 +908,7 @@ static void mtk_pcie_power_down(struct m
 119
 120         phy_power_off(pcie->phy);
 121         phy_exit(pcie->phy);
 122 -       reset_control_assert(pcie->phy_reset);
 123 +       reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 124  }
 125
 126  static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 127 @@ -909,10 +920,16 @@ static int mtk_pcie_setup(struct mtk_gen
 128                 return err;
 129
 130         /*
 131 +        * Deassert the line in order to avoid unbalance in deassert_count
 132 +        * counter since the bulk is shared.
 133 +        */
 134 +       reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 135 +       /*
 136          * The controller may have been left out of reset by the bootloader
 137          * so make sure that we get a clean start by asserting resets here.
 138          */
 139 -       reset_control_assert(pcie->phy_reset);
 140 +       reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets);
 141 +
 142         reset_control_assert(pcie->mac_reset);
 143         usleep_range(10, 20);
 144
 145 @@ -1090,6 +1107,10 @@ static const struct dev_pm_ops mtk_pcie_
 146
 147  static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
 148         .power_up = mtk_pcie_power_up,
 149 +       .phy_resets = {
 150 +               .id[0] = "phy",
 151 +               .num_resets = 1,
 152 +       },
 153  };
 154
 155  static const struct of_device_id mtk_pcie_of_match[] = {