git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From af7ec140ddc1815bc462109792d95bcad05cfbc4 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Reichel <sebastian.reichel@collabora.com>
   3 Date: Tue, 9 Apr 2024 00:50:36 +0200
   4 Subject: [PATCH] arm64: dts: rockchip: add upper USB3 port to rock-5a
   5
   6 Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from
   7 Radxa Rock 5 Model A. The lower one is already supported.
   8
   9 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  10 Link: https://lore.kernel.org/r/20240408225109.128953-10-sebastian.reichel@collabora.com
  11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  12 ---
  13  .../boot/dts/rockchip/rk3588s-rock-5a.dts      | 18 ++++++++++++++++++
  14  1 file changed, 18 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
  17 +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
  18 @@ -698,6 +698,14 @@
  19         };
  20  };
  21
  22 +&u2phy0 {
  23 +       status = "okay";
  24 +};
  25 +
  26 +&u2phy0_otg {
  27 +       status = "okay";
  28 +};
  29 +
  30  &u2phy2 {
  31         status = "okay";
  32  };
  33 @@ -721,6 +729,11 @@
  34         status = "okay";
  35  };
  36
  37 +&usbdp_phy0 {
  38 +       status = "okay";
  39 +       rockchip,dp-lane-mux = <2 3>;
  40 +};
  41 +
  42  &usb_host0_ehci {
  43         status = "okay";
  44         pinctrl-names = "default";
  45 @@ -731,6 +744,11 @@
  46         status = "okay";
  47  };
  48
  49 +&usb_host0_xhci {
  50 +       dr_mode = "host";
  51 +       status = "okay";
  52 +};
  53 +
  54  &usb_host1_ehci {
  55         status = "okay";
  56  };