git.openwrt.org Git - openwrt/staging/thess.git/blob

   1 From c31d1cdd7bff1d2c13d435bb9d0c76bfaa332097 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Tue, 12 Nov 2024 01:08:49 +0100
   4 Subject: [PATCH 1/6] clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK}
   5  configuration
   6
   7 REG_PCIE*_MEM and REG_PCIE*_MEM_MASK regs (PBUS_CSR memory region) are not
   8 part of the scu block on the EN7581 SoC and they are used to select the
   9 PCIE ports on the PBUS, so remove this configuration from the clock driver
  10 and set these registers in the PCIE host driver instead.
  11 This patch does not introduce any backward incompatibility since the dts
  12 for EN7581 SoC is not upstream yet.
  13
  14 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  15 Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-2-8ada5e394ae4@kernel.org
  16 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  17 ---
  18  drivers/clk/clk-en7523.c | 18 ------------------
  19  1 file changed, 18 deletions(-)
  20
  21 --- a/drivers/clk/clk-en7523.c
  22 +++ b/drivers/clk/clk-en7523.c
  23 @@ -31,12 +31,6 @@
  24  #define   REG_RESET_CONTROL_PCIE1      BIT(27)
  25  #define   REG_RESET_CONTROL_PCIE2      BIT(26)
  26  /* EN7581 */
  27 -#define REG_PCIE0_MEM                  0x00
  28 -#define REG_PCIE0_MEM_MASK             0x04
  29 -#define REG_PCIE1_MEM                  0x08
  30 -#define REG_PCIE1_MEM_MASK             0x0c
  31 -#define REG_PCIE2_MEM                  0x10
  32 -#define REG_PCIE2_MEM_MASK             0x14
  33  #define REG_NP_SCU_PCIC                        0x88
  34  #define REG_NP_SCU_SSTR                        0x9c
  35  #define REG_PCIE_XSI0_SEL_MASK         GENMASK(14, 13)
  36 @@ -415,26 +409,14 @@ static void en7581_pci_disable(struct cl
  37  static int en7581_clk_hw_init(struct platform_device *pdev,
  38                               void __iomem *np_base)
  39  {
  40 -       void __iomem *pb_base;
  41         u32 val;
  42
  43 -       pb_base = devm_platform_ioremap_resource(pdev, 3);
  44 -       if (IS_ERR(pb_base))
  45 -               return PTR_ERR(pb_base);
  46 -
  47         val = readl(np_base + REG_NP_SCU_SSTR);
  48         val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
  49         writel(val, np_base + REG_NP_SCU_SSTR);
  50         val = readl(np_base + REG_NP_SCU_PCIC);
  51         writel(val | 3, np_base + REG_NP_SCU_PCIC);
  52
  53 -       writel(0x20000000, pb_base + REG_PCIE0_MEM);
  54 -       writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
  55 -       writel(0x24000000, pb_base + REG_PCIE1_MEM);
  56 -       writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
  57 -       writel(0x28000000, pb_base + REG_PCIE2_MEM);
  58 -       writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
  59 -
  60         return 0;
  61  }
  62