git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 5ef0b04d30efff8f171e30bfbe876c00e3b9036a Mon Sep 17 00:00:00 2001
   2 From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
   3 Date: Fri, 9 May 2025 09:49:04 +0800
   4 Subject: [PATCH] net: ethernet: mtk_eth_soc: revise hardware configuration for
   5  mt7987
   6
   7 Change hardware configuration for the MT7987.
   8  - Enable PSE drop mechanism when the WDMA Rx ring full
   9  - Enable PSE no-drop mechanism for packets from the WDMA Tx
  10
  11 Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
  12 ---
  13  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 +++++++++++++--------
  14  1 file changed, 31 insertions(+), 18 deletions(-)
  15
  16 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  17 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  18 @@ -4445,27 +4445,40 @@ static int mtk_hw_init(struct mtk_eth *e
  19                 mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
  20                         PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ);
  21
  22 -               /* PSE free buffer drop threshold */
  23 -               mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
  24 -
  25 -               /* PSE should not drop port8, port9 and port13 packets from
  26 -                * WDMA Tx
  27 -                */
  28 -               mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
  29 -
  30 -               /* PSE should drop packets to port8, port9 and port13 on WDMA Rx
  31 -                * ring full
  32 -                */
  33 -               mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
  34 -               mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
  35 -               mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
  36 -
  37 -               /* GDM and CDM Threshold */
  38 -               mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
  39 -               mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
  40 -
  41 -               /* Disable GDM1 RX CRC stripping */
  42 -               mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
  43 +               if (eth->soc->caps == MT7988_CAPS) {
  44 +                       /* PSE free buffer drop threshold */
  45 +                       mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
  46 +
  47 +                       /* PSE should not drop port8, port9 and port13 packets
  48 +                        * from WDMA Tx
  49 +                        */
  50 +                       mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
  51 +
  52 +                       /* PSE should drop packets to port8, port9 and port13
  53 +                        * on WDMA Rx ring full
  54 +                        */
  55 +                       mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
  56 +                       mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
  57 +                       mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
  58 +
  59 +                       /* GDM and CDM Threshold */
  60 +                       mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
  61 +                       mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
  62 +               } else if (eth->soc->caps == MT7987_CAPS) {
  63 +                       /* PSE should not drop port8 packets from WDMA Tx */
  64 +                       mtk_w32(eth, 0x00000100, PSE_DROP_CFG);
  65 +
  66 +                       /* PSE should drop packets to port8 on WDMA Rx ring
  67 +                        * full
  68 +                        */
  69 +                       mtk_w32(eth, 0x00000100, PSE_PPE_DROP(0));
  70 +                       mtk_w32(eth, 0x00000100, PSE_PPE_DROP(1));
  71 +               }
  72 +
  73 +               if (MTK_HAS_CAPS(eth->soc->caps, MTK_ESW)) {
  74 +                       /* Disable GDM1 RX CRC stripping */
  75 +                       mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0));
  76 +               }
  77
  78                 /* PSE GDM3 MIB counter has incorrect hw default values,
  79                  * so the driver ought to read clear the values beforehand