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1 From 7e06c3dbfa5f1e39eba92eb79d854fab2a7ad5fe Mon Sep 17 00:00:00 2001
2 From: Sky Huang <skylake.huang@mediatek.com>
3 Date: Thu, 13 Feb 2025 16:05:49 +0800
4 Subject: [PATCH 10/20] net: phy: mediatek: Change to more meaningful macros
5
6 Replace magic number with more meaningful macros in mtk-ge.c.
7 Also, move some common macros into mtk-phy-lib.c.
8
9 Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
10 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
11 Link: https://patch.msgid.link/20250213080553.921434-2-SkyLake.Huang@mediatek.com
12 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
13 ---
14 drivers/net/phy/mediatek/mtk-ge-soc.c | 1 -
15 drivers/net/phy/mediatek/mtk-ge.c | 71 +++++++++++++++++++++------
16 drivers/net/phy/mediatek/mtk.h | 2 +
17 3 files changed, 57 insertions(+), 17 deletions(-)
18
19 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c
20 +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
21 @@ -24,7 +24,6 @@
22 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
23
24 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
25 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
26
27 #define ANALOG_INTERNAL_OPERATION_MAX_US 20
28 #define TXRESERVE_MIN 0
29 --- a/drivers/net/phy/mediatek/mtk-ge.c
30 +++ b/drivers/net/phy/mediatek/mtk-ge.c
31 @@ -8,18 +8,38 @@
32 #define MTK_GPHY_ID_MT7530 0x03a29412
33 #define MTK_GPHY_ID_MT7531 0x03a29441
34
35 -#define MTK_EXT_PAGE_ACCESS 0x1f
36 -#define MTK_PHY_PAGE_STANDARD 0x0000
37 -#define MTK_PHY_PAGE_EXTENDED 0x0001
38 -#define MTK_PHY_PAGE_EXTENDED_2 0x0002
39 -#define MTK_PHY_PAGE_EXTENDED_3 0x0003
40 -#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
41 -#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
42 +#define MTK_PHY_PAGE_EXTENDED_1 0x0001
43 +#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
44 +#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
45 +
46 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002
47 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003
48 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
49 +
50 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
51 +
52 +/* Registers on MDIO_MMD_VEND1 */
53 +#define MTK_PHY_GBE_MODE_TX_DELAY_SEL 0x13
54 +#define MTK_PHY_TEST_MODE_TX_DELAY_SEL 0x14
55 +#define MTK_TX_DELAY_PAIR_B_MASK GENMASK(10, 8)
56 +#define MTK_TX_DELAY_PAIR_D_MASK GENMASK(2, 0)
57 +
58 +#define MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL 0xa6
59 +#define MTK_MCC_NEARECHO_OFFSET_MASK GENMASK(15, 8)
60 +
61 +#define MTK_PHY_RXADC_CTRL_RG7 0xc6
62 +#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
63 +
64 +#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123 0x123
65 +#define MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK GENMASK(15, 8)
66 +#define MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK GENMASK(7, 0)
67
68 static void mtk_gephy_config_init(struct phy_device *phydev)
69 {
70 /* Enable HW auto downshift */
71 - phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
72 + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
73 + MTK_PHY_AUX_CTRL_AND_STATUS,
74 + 0, MTK_PHY_ENABLE_DOWNSHIFT);
75
76 /* Increase SlvDPSready time */
77 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
78 @@ -29,10 +49,20 @@ static void mtk_gephy_config_init(struct
79 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
80
81 /* Adjust 100_mse_threshold */
82 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
83 -
84 - /* Disable mcc */
85 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
86 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
87 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG123,
88 + MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK |
89 + MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
90 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_LO_THRESH100_MASK,
91 + 0xff) |
92 + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH100_MASK,
93 + 0xff));
94 +
95 + /* If echo time is narrower than 0x3, it will be regarded as noise */
96 + phy_modify_mmd(phydev, MDIO_MMD_VEND1,
97 + MTK_PHY_MCC_CTRL_AND_TX_POWER_CTRL,
98 + MTK_MCC_NEARECHO_OFFSET_MASK,
99 + FIELD_PREP(MTK_MCC_NEARECHO_OFFSET_MASK, 0x3));
100 }
101
102 static int mt7530_phy_config_init(struct phy_device *phydev)
103 @@ -40,7 +70,8 @@ static int mt7530_phy_config_init(struct
104 mtk_gephy_config_init(phydev);
105
106 /* Increase post_update_timer */
107 - phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
108 + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3,
109 + MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11, 0x4b);
110
111 return 0;
112 }
113 @@ -51,11 +82,19 @@ static int mt7531_phy_config_init(struct
114
115 /* PHY link down power saving enable */
116 phy_set_bits(phydev, 0x17, BIT(4));
117 - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
118 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
119 + MTK_PHY_DA_AD_BUF_BIAS_LP_MASK,
120 + FIELD_PREP(MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3));
121
122 /* Set TX Pair delay selection */
123 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
124 - phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
125 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_GBE_MODE_TX_DELAY_SEL,
126 + MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
127 + FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
128 + FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
129 + phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TEST_MODE_TX_DELAY_SEL,
130 + MTK_TX_DELAY_PAIR_B_MASK | MTK_TX_DELAY_PAIR_D_MASK,
131 + FIELD_PREP(MTK_TX_DELAY_PAIR_B_MASK, 0x4) |
132 + FIELD_PREP(MTK_TX_DELAY_PAIR_D_MASK, 0x4));
133
134 return 0;
135 }
136 --- a/drivers/net/phy/mediatek/mtk.h
137 +++ b/drivers/net/phy/mediatek/mtk.h
138 @@ -9,6 +9,8 @@
139 #define _MTK_EPHY_H_
140
141 #define MTK_EXT_PAGE_ACCESS 0x1f
142 +#define MTK_PHY_PAGE_STANDARD 0x0000
143 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
144
145 /* Registers on MDIO_MMD_VEND2 */
146 #define MTK_PHY_LED0_ON_CTRL 0x24
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