git.openwrt.org Git - openwrt/staging/linusw.git/blob

   1 From e88f03230dc07aa3293b6aeb078bd27370bb2594 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Wed, 20 Dec 2023 23:17:24 +0100
   4 Subject: [PATCH] clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple
   5  conf
   6
   7 Rework nss_port5/6 to use the new multiple configuration implementation
   8 and correctly fix the clocks for these port under some corner case.
   9
  10 This is particularly relevant for device that have 2.5G or 10G port
  11 connected to port5 or port 6 on ipq8074. As the parent are shared
  12 across multiple port it may be required to select the correct
  13 configuration to accomplish the desired clock. Without this patch such
  14 port doesn't work in some specific ethernet speed as the clock will be
  15 set to the wrong frequency as we just select the first configuration for
  16 the related frequency instead of selecting the best one.
  17
  18 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  19 Acked-by: Stephen Boyd <sboyd@kernel.org>
  20 Link: https://lore.kernel.org/r/20231220221724.3822-4-ansuelsmth@gmail.com
  21 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  22 ---
  23  drivers/clk/qcom/gcc-ipq8074.c | 120 +++++++++++++++++++++------------
  24  1 file changed, 76 insertions(+), 44 deletions(-)
  25
  26 --- a/drivers/clk/qcom/gcc-ipq8074.c
  27 +++ b/drivers/clk/qcom/gcc-ipq8074.c
  28 @@ -1677,15 +1677,23 @@ static struct clk_regmap_div nss_port4_t
  29         },
  30  };
  31
  32 -static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
  33 -       F(19200000, P_XO, 1, 0, 0),
  34 -       F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
  35 -       F(25000000, P_UNIPHY0_RX, 5, 0, 0),
  36 -       F(78125000, P_UNIPHY1_RX, 4, 0, 0),
  37 -       F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
  38 -       F(125000000, P_UNIPHY0_RX, 1, 0, 0),
  39 -       F(156250000, P_UNIPHY1_RX, 2, 0, 0),
  40 -       F(312500000, P_UNIPHY1_RX, 1, 0, 0),
  41 +static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
  42 +       C(P_UNIPHY1_RX, 12.5, 0, 0),
  43 +       C(P_UNIPHY0_RX, 5, 0, 0),
  44 +};
  45 +
  46 +static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
  47 +       C(P_UNIPHY1_RX, 2.5, 0, 0),
  48 +       C(P_UNIPHY0_RX, 1, 0, 0),
  49 +};
  50 +
  51 +static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
  52 +       FMS(19200000, P_XO, 1, 0, 0),
  53 +       FM(25000000, ftbl_nss_port5_rx_clk_src_25),
  54 +       FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
  55 +       FM(125000000, ftbl_nss_port5_rx_clk_src_125),
  56 +       FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
  57 +       FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
  58         { }
  59  };
  60
  61 @@ -1712,14 +1720,14 @@ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32
  62
  63  static struct clk_rcg2 nss_port5_rx_clk_src = {
  64         .cmd_rcgr = 0x68060,
  65 -       .freq_tbl = ftbl_nss_port5_rx_clk_src,
  66 +       .freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
  67         .hid_width = 5,
  68         .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
  69         .clkr.hw.init = &(struct clk_init_data){
  70                 .name = "nss_port5_rx_clk_src",
  71                 .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
  72                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
  73 -               .ops = &clk_rcg2_ops,
  74 +               .ops = &clk_rcg2_fm_ops,
  75         },
  76  };
  77
  78 @@ -1739,15 +1747,23 @@ static struct clk_regmap_div nss_port5_r
  79         },
  80  };
  81
  82 -static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
  83 -       F(19200000, P_XO, 1, 0, 0),
  84 -       F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
  85 -       F(25000000, P_UNIPHY0_TX, 5, 0, 0),
  86 -       F(78125000, P_UNIPHY1_TX, 4, 0, 0),
  87 -       F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
  88 -       F(125000000, P_UNIPHY0_TX, 1, 0, 0),
  89 -       F(156250000, P_UNIPHY1_TX, 2, 0, 0),
  90 -       F(312500000, P_UNIPHY1_TX, 1, 0, 0),
  91 +static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
  92 +       C(P_UNIPHY1_TX, 12.5, 0, 0),
  93 +       C(P_UNIPHY0_TX, 5, 0, 0),
  94 +};
  95 +
  96 +static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
  97 +       C(P_UNIPHY1_TX, 2.5, 0, 0),
  98 +       C(P_UNIPHY0_TX, 1, 0, 0),
  99 +};
 100 +
 101 +static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
 102 +       FMS(19200000, P_XO, 1, 0, 0),
 103 +       FM(25000000, ftbl_nss_port5_tx_clk_src_25),
 104 +       FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
 105 +       FM(125000000, ftbl_nss_port5_tx_clk_src_125),
 106 +       FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
 107 +       FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
 108         { }
 109  };
 110
 111 @@ -1774,14 +1790,14 @@ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32
 112
 113  static struct clk_rcg2 nss_port5_tx_clk_src = {
 114         .cmd_rcgr = 0x68068,
 115 -       .freq_tbl = ftbl_nss_port5_tx_clk_src,
 116 +       .freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
 117         .hid_width = 5,
 118         .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
 119         .clkr.hw.init = &(struct clk_init_data){
 120                 .name = "nss_port5_tx_clk_src",
 121                 .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
 122                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
 123 -               .ops = &clk_rcg2_ops,
 124 +               .ops = &clk_rcg2_fm_ops,
 125         },
 126  };
 127
 128 @@ -1801,15 +1817,23 @@ static struct clk_regmap_div nss_port5_t
 129         },
 130  };
 131
 132 -static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
 133 -       F(19200000, P_XO, 1, 0, 0),
 134 -       F(25000000, P_UNIPHY2_RX, 5, 0, 0),
 135 -       F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
 136 -       F(78125000, P_UNIPHY2_RX, 4, 0, 0),
 137 -       F(125000000, P_UNIPHY2_RX, 1, 0, 0),
 138 -       F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
 139 -       F(156250000, P_UNIPHY2_RX, 2, 0, 0),
 140 -       F(312500000, P_UNIPHY2_RX, 1, 0, 0),
 141 +static const struct freq_conf ftbl_nss_port6_rx_clk_src_25[] = {
 142 +       C(P_UNIPHY2_RX, 5, 0, 0),
 143 +       C(P_UNIPHY2_RX, 12.5, 0, 0),
 144 +};
 145 +
 146 +static const struct freq_conf ftbl_nss_port6_rx_clk_src_125[] = {
 147 +       C(P_UNIPHY2_RX, 1, 0, 0),
 148 +       C(P_UNIPHY2_RX, 2.5, 0, 0),
 149 +};
 150 +
 151 +static const struct freq_multi_tbl ftbl_nss_port6_rx_clk_src[] = {
 152 +       FMS(19200000, P_XO, 1, 0, 0),
 153 +       FM(25000000, ftbl_nss_port6_rx_clk_src_25),
 154 +       FMS(78125000, P_UNIPHY2_RX, 4, 0, 0),
 155 +       FM(125000000, ftbl_nss_port6_rx_clk_src_125),
 156 +       FMS(156250000, P_UNIPHY2_RX, 2, 0, 0),
 157 +       FMS(312500000, P_UNIPHY2_RX, 1, 0, 0),
 158         { }
 159  };
 160
 161 @@ -1831,14 +1855,14 @@ static const struct parent_map gcc_xo_un
 162
 163  static struct clk_rcg2 nss_port6_rx_clk_src = {
 164         .cmd_rcgr = 0x68070,
 165 -       .freq_tbl = ftbl_nss_port6_rx_clk_src,
 166 +       .freq_multi_tbl = ftbl_nss_port6_rx_clk_src,
 167         .hid_width = 5,
 168         .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
 169         .clkr.hw.init = &(struct clk_init_data){
 170                 .name = "nss_port6_rx_clk_src",
 171                 .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
 172                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
 173 -               .ops = &clk_rcg2_ops,
 174 +               .ops = &clk_rcg2_fm_ops,
 175         },
 176  };
 177
 178 @@ -1858,15 +1882,23 @@ static struct clk_regmap_div nss_port6_r
 179         },
 180  };
 181
 182 -static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
 183 -       F(19200000, P_XO, 1, 0, 0),
 184 -       F(25000000, P_UNIPHY2_TX, 5, 0, 0),
 185 -       F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
 186 -       F(78125000, P_UNIPHY2_TX, 4, 0, 0),
 187 -       F(125000000, P_UNIPHY2_TX, 1, 0, 0),
 188 -       F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
 189 -       F(156250000, P_UNIPHY2_TX, 2, 0, 0),
 190 -       F(312500000, P_UNIPHY2_TX, 1, 0, 0),
 191 +static const struct freq_conf ftbl_nss_port6_tx_clk_src_25[] = {
 192 +       C(P_UNIPHY2_TX, 5, 0, 0),
 193 +       C(P_UNIPHY2_TX, 12.5, 0, 0),
 194 +};
 195 +
 196 +static const struct freq_conf ftbl_nss_port6_tx_clk_src_125[] = {
 197 +       C(P_UNIPHY2_TX, 1, 0, 0),
 198 +       C(P_UNIPHY2_TX, 2.5, 0, 0),
 199 +};
 200 +
 201 +static const struct freq_multi_tbl ftbl_nss_port6_tx_clk_src[] = {
 202 +       FMS(19200000, P_XO, 1, 0, 0),
 203 +       FM(25000000, ftbl_nss_port6_tx_clk_src_25),
 204 +       FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
 205 +       FM(125000000, ftbl_nss_port6_tx_clk_src_125),
 206 +       FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
 207 +       FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
 208         { }
 209  };
 210
 211 @@ -1888,14 +1920,14 @@ static const struct parent_map gcc_xo_un
 212
 213  static struct clk_rcg2 nss_port6_tx_clk_src = {
 214         .cmd_rcgr = 0x68078,
 215 -       .freq_tbl = ftbl_nss_port6_tx_clk_src,
 216 +       .freq_multi_tbl = ftbl_nss_port6_tx_clk_src,
 217         .hid_width = 5,
 218         .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
 219         .clkr.hw.init = &(struct clk_init_data){
 220                 .name = "nss_port6_tx_clk_src",
 221                 .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
 222                 .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
 223 -               .ops = &clk_rcg2_ops,
 224 +               .ops = &clk_rcg2_fm_ops,
 225         },
 226  };
 227