4bf0598c360eb248490dbf988c7afc50d2d2b912
[openwrt/staging/linusw.git] /
1 From: Gabor Juhos <j4g8y7@gmail.com>
2 Subject: [PATCH] clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
3 Date: Tue, 26 Mar 2024 14:34:11 +0100
4
5 According to ipq5018.dtsi, the maximum supported rate by the
6 CPU is 1.008 GHz on the IPQ5018 platform, however the current
7 configuration of the PLL results in 1.2 GHz rate.
8
9 Change the 'L' value in the PLL configuration to limit the
10 rate to 1.008 GHz. The downstream kernel also uses the same
11 value [1]. Also add a comment to indicate the desired
12 frequency.
13
14 [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4/drivers/clk/qcom/apss-ipq5018.c?ref_type=heads#L151
15
16 Fixes: 50492f929486 ("clk: qcom: apss-ipq-pll: add support for IPQ5018")
17 Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
18 ---
19 drivers/clk/qcom/apss-ipq-pll.c | 3 ++-
20 1 file changed, 2 insertions(+), 1 deletion(-)
21
22 --- a/drivers/clk/qcom/apss-ipq-pll.c
23 +++ b/drivers/clk/qcom/apss-ipq-pll.c
24 @@ -97,7 +97,7 @@ static struct clk_alpha_pll ipq_pll_stro
25 };
26
27 static const struct alpha_pll_config ipq5018_pll_config = {
28 - .l = 0x32,
29 + .l = 0x2a,
30 .config_ctl_val = 0x4001075b,
31 .config_ctl_hi_val = 0x304,
32 .main_output_mask = BIT(0),