git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001
   2 From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
   3 Date: Tue, 4 Feb 2025 14:40:07 +0200
   4 Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
   5
   6 Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
   7 provider support"), the HDMI PHY PLL can be used as an alternative and
   8 more accurate pixel clock source for VOP2 to improve display modes
   9 handling on RK3588 SoC.
  10
  11 Add the missing #clock-cells property to allow using the clock provider
  12 functionality of HDMI0 PHY.
  13
  14 Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
  15 Tested-by: FUKAUMI Naoki <naoki@radxa.com>
  16 Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
  17 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  18
  19 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  20 +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  21 @@ -2813,6 +2813,7 @@
  22                 reg = <0x0 0xfed60000 0x0 0x2000>;
  23                 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
  24                 clock-names = "ref", "apb";
  25 +               #clock-cells = <0>;
  26                 #phy-cells = <0>;
  27                 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
  28                          <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,