git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From 7aa291962f4c3b7afb9a12fa60b406b95e5eacb4 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Thu, 27 Jun 2024 13:04:22 +0200
   4 Subject: [PATCH] dt-bindings: clock: airoha: Add reset support to EN7581 clock
   5  binding
   6
   7 Introduce reset capability to EN7581 device-tree clock binding
   8 documentation. Add reset register mapping between misc scu and pb scu
   9 ones in order to follow the memory order. This change is not
  10 introducing any backward compatibility issue since the EN7581 dts is not
  11 upstream yet.
  12
  13 Fixes: 0a382be005cf ("dt-bindings: clock: airoha: add EN7581 binding")
  14 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  15 Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
  16 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  17 Link: https://lore.kernel.org/r/28fef3e83062d5d71e7b4be4b47583f851a15bf8.1719485847.git.lorenzo@kernel.org
  18 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  19 ---
  20  .../bindings/clock/airoha,en7523-scu.yaml     | 25 ++++++-
  21  .../dt-bindings/reset/airoha,en7581-reset.h   | 66 +++++++++++++++++++
  22  2 files changed, 90 insertions(+), 1 deletion(-)
  23  create mode 100644 include/dt-bindings/reset/airoha,en7581-reset.h
  24
  25 --- /dev/null
  26 +++ b/include/dt-bindings/reset/airoha,en7581-reset.h
  27 @@ -0,0 +1,66 @@
  28 +// SPDX-License-Identifier: GPL-2.0-only
  29 +/*
  30 + * Copyright (c) 2024 AIROHA Inc
  31 + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
  32 + */
  33 +
  34 +#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
  35 +#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_
  36 +
  37 +/* RST_CTRL2 */
  38 +#define EN7581_XPON_PHY_RST             0
  39 +#define EN7581_CPU_TIMER2_RST           1
  40 +#define EN7581_HSUART_RST               2
  41 +#define EN7581_UART4_RST                3
  42 +#define EN7581_UART5_RST                4
  43 +#define EN7581_I2C2_RST                         5
  44 +#define EN7581_XSI_MAC_RST              6
  45 +#define EN7581_XSI_PHY_RST              7
  46 +#define EN7581_NPU_RST                  8
  47 +#define EN7581_I2S_RST                  9
  48 +#define EN7581_TRNG_RST                        10
  49 +#define EN7581_TRNG_MSTART_RST         11
  50 +#define EN7581_DUAL_HSI0_RST           12
  51 +#define EN7581_DUAL_HSI1_RST           13
  52 +#define EN7581_HSI_RST                 14
  53 +#define EN7581_DUAL_HSI0_MAC_RST       15
  54 +#define EN7581_DUAL_HSI1_MAC_RST       16
  55 +#define EN7581_HSI_MAC_RST             17
  56 +#define EN7581_WDMA_RST                        18
  57 +#define EN7581_WOE0_RST                        19
  58 +#define EN7581_WOE1_RST                        20
  59 +#define EN7581_HSDMA_RST               21
  60 +#define EN7581_TDMA_RST                        22
  61 +#define EN7581_EMMC_RST                        23
  62 +#define EN7581_SOE_RST                 24
  63 +#define EN7581_PCIE2_RST               25
  64 +#define EN7581_XFP_MAC_RST             26
  65 +#define EN7581_USB_HOST_P1_RST         27
  66 +#define EN7581_USB_HOST_P1_U3_PHY_RST  28
  67 +/* RST_CTRL1 */
  68 +#define EN7581_PCM1_ZSI_ISI_RST                29
  69 +#define EN7581_FE_PDMA_RST             30
  70 +#define EN7581_FE_QDMA_RST             31
  71 +#define EN7581_PCM_SPIWP_RST           32
  72 +#define EN7581_CRYPTO_RST              33
  73 +#define EN7581_TIMER_RST               34
  74 +#define EN7581_PCM1_RST                        35
  75 +#define EN7581_UART_RST                        36
  76 +#define EN7581_GPIO_RST                        37
  77 +#define EN7581_GDMA_RST                        38
  78 +#define EN7581_I2C_MASTER_RST          39
  79 +#define EN7581_PCM2_ZSI_ISI_RST                40
  80 +#define EN7581_SFC_RST                 41
  81 +#define EN7581_UART2_RST               42
  82 +#define EN7581_GDMP_RST                        43
  83 +#define EN7581_FE_RST                  44
  84 +#define EN7581_USB_HOST_P0_RST         45
  85 +#define EN7581_GSW_RST                 46
  86 +#define EN7581_SFC2_PCM_RST            47
  87 +#define EN7581_PCIE0_RST               48
  88 +#define EN7581_PCIE1_RST               49
  89 +#define EN7581_CPU_TIMER_RST           50
  90 +#define EN7581_PCIE_HB_RST             51
  91 +#define EN7581_XPON_MAC_RST            52
  92 +
  93 +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */