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1 From ec663d9a82bf4d16721f6b1fc29df4892ba6c088 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Fri, 28 Feb 2025 11:54:12 +0100
4 Subject: [PATCH 04/15] net: airoha: Move register definitions in airoha_regs.h
5
6 Move common airoha_eth register definitions in airoha_regs.h in order
7 to reuse them for Packet Processor Engine (PPE) codebase.
8 PPE module is used to enable support for flowtable hw offloading in
9 airoha_eth driver.
10
11 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
12 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
13 ---
14 drivers/net/ethernet/airoha/airoha_eth.c | 659 +--------------------
15 drivers/net/ethernet/airoha/airoha_regs.h | 670 ++++++++++++++++++++++
16 2 files changed, 671 insertions(+), 658 deletions(-)
17 create mode 100644 drivers/net/ethernet/airoha/airoha_regs.h
18
19 --- a/drivers/net/ethernet/airoha/airoha_eth.c
20 +++ b/drivers/net/ethernet/airoha/airoha_eth.c
21 @@ -13,666 +13,9 @@
22 #include <net/pkt_cls.h>
23 #include <uapi/linux/ppp_defs.h>
24
25 +#include "airoha_regs.h"
26 #include "airoha_eth.h"
27
28 -/* FE */
29 -#define PSE_BASE 0x0100
30 -#define CSR_IFC_BASE 0x0200
31 -#define CDM1_BASE 0x0400
32 -#define GDM1_BASE 0x0500
33 -#define PPE1_BASE 0x0c00
34 -
35 -#define CDM2_BASE 0x1400
36 -#define GDM2_BASE 0x1500
37 -
38 -#define GDM3_BASE 0x1100
39 -#define GDM4_BASE 0x2500
40 -
41 -#define GDM_BASE(_n) \
42 - ((_n) == 4 ? GDM4_BASE : \
43 - (_n) == 3 ? GDM3_BASE : \
44 - (_n) == 2 ? GDM2_BASE : GDM1_BASE)
45 -
46 -#define REG_FE_DMA_GLO_CFG 0x0000
47 -#define FE_DMA_GLO_L2_SPACE_MASK GENMASK(7, 4)
48 -#define FE_DMA_GLO_PG_SZ_MASK BIT(3)
49 -
50 -#define REG_FE_RST_GLO_CFG 0x0004
51 -#define FE_RST_GDM4_MBI_ARB_MASK BIT(3)
52 -#define FE_RST_GDM3_MBI_ARB_MASK BIT(2)
53 -#define FE_RST_CORE_MASK BIT(0)
54 -
55 -#define REG_FE_WAN_MAC_H 0x0030
56 -#define REG_FE_LAN_MAC_H 0x0040
57 -
58 -#define REG_FE_MAC_LMIN(_n) ((_n) + 0x04)
59 -#define REG_FE_MAC_LMAX(_n) ((_n) + 0x08)
60 -
61 -#define REG_FE_CDM1_OQ_MAP0 0x0050
62 -#define REG_FE_CDM1_OQ_MAP1 0x0054
63 -#define REG_FE_CDM1_OQ_MAP2 0x0058
64 -#define REG_FE_CDM1_OQ_MAP3 0x005c
65 -
66 -#define REG_FE_PCE_CFG 0x0070
67 -#define PCE_DPI_EN_MASK BIT(2)
68 -#define PCE_KA_EN_MASK BIT(1)
69 -#define PCE_MC_EN_MASK BIT(0)
70 -
71 -#define REG_FE_PSE_QUEUE_CFG_WR 0x0080
72 -#define PSE_CFG_PORT_ID_MASK GENMASK(27, 24)
73 -#define PSE_CFG_QUEUE_ID_MASK GENMASK(20, 16)
74 -#define PSE_CFG_WR_EN_MASK BIT(8)
75 -#define PSE_CFG_OQRSV_SEL_MASK BIT(0)
76 -
77 -#define REG_FE_PSE_QUEUE_CFG_VAL 0x0084
78 -#define PSE_CFG_OQ_RSV_MASK GENMASK(13, 0)
79 -
80 -#define PSE_FQ_CFG 0x008c
81 -#define PSE_FQ_LIMIT_MASK GENMASK(14, 0)
82 -
83 -#define REG_FE_PSE_BUF_SET 0x0090
84 -#define PSE_SHARE_USED_LTHD_MASK GENMASK(31, 16)
85 -#define PSE_ALLRSV_MASK GENMASK(14, 0)
86 -
87 -#define REG_PSE_SHARE_USED_THD 0x0094
88 -#define PSE_SHARE_USED_MTHD_MASK GENMASK(31, 16)
89 -#define PSE_SHARE_USED_HTHD_MASK GENMASK(15, 0)
90 -
91 -#define REG_GDM_MISC_CFG 0x0148
92 -#define GDM2_RDM_ACK_WAIT_PREF_MASK BIT(9)
93 -#define GDM2_CHN_VLD_MODE_MASK BIT(5)
94 -
95 -#define REG_FE_CSR_IFC_CFG CSR_IFC_BASE
96 -#define FE_IFC_EN_MASK BIT(0)
97 -
98 -#define REG_FE_VIP_PORT_EN 0x01f0
99 -#define REG_FE_IFC_PORT_EN 0x01f4
100 -
101 -#define REG_PSE_IQ_REV1 (PSE_BASE + 0x08)
102 -#define PSE_IQ_RES1_P2_MASK GENMASK(23, 16)
103 -
104 -#define REG_PSE_IQ_REV2 (PSE_BASE + 0x0c)
105 -#define PSE_IQ_RES2_P5_MASK GENMASK(15, 8)
106 -#define PSE_IQ_RES2_P4_MASK GENMASK(7, 0)
107 -
108 -#define REG_FE_VIP_EN(_n) (0x0300 + ((_n) << 3))
109 -#define PATN_FCPU_EN_MASK BIT(7)
110 -#define PATN_SWP_EN_MASK BIT(6)
111 -#define PATN_DP_EN_MASK BIT(5)
112 -#define PATN_SP_EN_MASK BIT(4)
113 -#define PATN_TYPE_MASK GENMASK(3, 1)
114 -#define PATN_EN_MASK BIT(0)
115 -
116 -#define REG_FE_VIP_PATN(_n) (0x0304 + ((_n) << 3))
117 -#define PATN_DP_MASK GENMASK(31, 16)
118 -#define PATN_SP_MASK GENMASK(15, 0)
119 -
120 -#define REG_CDM1_VLAN_CTRL CDM1_BASE
121 -#define CDM1_VLAN_MASK GENMASK(31, 16)
122 -
123 -#define REG_CDM1_FWD_CFG (CDM1_BASE + 0x08)
124 -#define CDM1_VIP_QSEL_MASK GENMASK(24, 20)
125 -
126 -#define REG_CDM1_CRSN_QSEL(_n) (CDM1_BASE + 0x10 + ((_n) << 2))
127 -#define CDM1_CRSN_QSEL_REASON_MASK(_n) \
128 - GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3))
129 -
130 -#define REG_CDM2_FWD_CFG (CDM2_BASE + 0x08)
131 -#define CDM2_OAM_QSEL_MASK GENMASK(31, 27)
132 -#define CDM2_VIP_QSEL_MASK GENMASK(24, 20)
133 -
134 -#define REG_CDM2_CRSN_QSEL(_n) (CDM2_BASE + 0x10 + ((_n) << 2))
135 -#define CDM2_CRSN_QSEL_REASON_MASK(_n) \
136 - GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3))
137 -
138 -#define REG_GDM_FWD_CFG(_n) GDM_BASE(_n)
139 -#define GDM_DROP_CRC_ERR BIT(23)
140 -#define GDM_IP4_CKSUM BIT(22)
141 -#define GDM_TCP_CKSUM BIT(21)
142 -#define GDM_UDP_CKSUM BIT(20)
143 -#define GDM_UCFQ_MASK GENMASK(15, 12)
144 -#define GDM_BCFQ_MASK GENMASK(11, 8)
145 -#define GDM_MCFQ_MASK GENMASK(7, 4)
146 -#define GDM_OCFQ_MASK GENMASK(3, 0)
147 -
148 -#define REG_GDM_INGRESS_CFG(_n) (GDM_BASE(_n) + 0x10)
149 -#define GDM_INGRESS_FC_EN_MASK BIT(1)
150 -#define GDM_STAG_EN_MASK BIT(0)
151 -
152 -#define REG_GDM_LEN_CFG(_n) (GDM_BASE(_n) + 0x14)
153 -#define GDM_SHORT_LEN_MASK GENMASK(13, 0)
154 -#define GDM_LONG_LEN_MASK GENMASK(29, 16)
155 -
156 -#define REG_FE_CPORT_CFG (GDM1_BASE + 0x40)
157 -#define FE_CPORT_PAD BIT(26)
158 -#define FE_CPORT_PORT_XFC_MASK BIT(25)
159 -#define FE_CPORT_QUEUE_XFC_MASK BIT(24)
160 -
161 -#define REG_FE_GDM_MIB_CLEAR(_n) (GDM_BASE(_n) + 0xf0)
162 -#define FE_GDM_MIB_RX_CLEAR_MASK BIT(1)
163 -#define FE_GDM_MIB_TX_CLEAR_MASK BIT(0)
164 -
165 -#define REG_FE_GDM1_MIB_CFG (GDM1_BASE + 0xf4)
166 -#define FE_STRICT_RFC2819_MODE_MASK BIT(31)
167 -#define FE_GDM1_TX_MIB_SPLIT_EN_MASK BIT(17)
168 -#define FE_GDM1_RX_MIB_SPLIT_EN_MASK BIT(16)
169 -#define FE_TX_MIB_ID_MASK GENMASK(15, 8)
170 -#define FE_RX_MIB_ID_MASK GENMASK(7, 0)
171 -
172 -#define REG_FE_GDM_TX_OK_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x104)
173 -#define REG_FE_GDM_TX_OK_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x10c)
174 -#define REG_FE_GDM_TX_ETH_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x110)
175 -#define REG_FE_GDM_TX_ETH_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x114)
176 -#define REG_FE_GDM_TX_ETH_DROP_CNT(_n) (GDM_BASE(_n) + 0x118)
177 -#define REG_FE_GDM_TX_ETH_BC_CNT(_n) (GDM_BASE(_n) + 0x11c)
178 -#define REG_FE_GDM_TX_ETH_MC_CNT(_n) (GDM_BASE(_n) + 0x120)
179 -#define REG_FE_GDM_TX_ETH_RUNT_CNT(_n) (GDM_BASE(_n) + 0x124)
180 -#define REG_FE_GDM_TX_ETH_LONG_CNT(_n) (GDM_BASE(_n) + 0x128)
181 -#define REG_FE_GDM_TX_ETH_E64_CNT_L(_n) (GDM_BASE(_n) + 0x12c)
182 -#define REG_FE_GDM_TX_ETH_L64_CNT_L(_n) (GDM_BASE(_n) + 0x130)
183 -#define REG_FE_GDM_TX_ETH_L127_CNT_L(_n) (GDM_BASE(_n) + 0x134)
184 -#define REG_FE_GDM_TX_ETH_L255_CNT_L(_n) (GDM_BASE(_n) + 0x138)
185 -#define REG_FE_GDM_TX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x13c)
186 -#define REG_FE_GDM_TX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x140)
187 -
188 -#define REG_FE_GDM_RX_OK_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x148)
189 -#define REG_FE_GDM_RX_FC_DROP_CNT(_n) (GDM_BASE(_n) + 0x14c)
190 -#define REG_FE_GDM_RX_RC_DROP_CNT(_n) (GDM_BASE(_n) + 0x150)
191 -#define REG_FE_GDM_RX_OVERFLOW_DROP_CNT(_n) (GDM_BASE(_n) + 0x154)
192 -#define REG_FE_GDM_RX_ERROR_DROP_CNT(_n) (GDM_BASE(_n) + 0x158)
193 -#define REG_FE_GDM_RX_OK_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x15c)
194 -#define REG_FE_GDM_RX_ETH_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x160)
195 -#define REG_FE_GDM_RX_ETH_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x164)
196 -#define REG_FE_GDM_RX_ETH_DROP_CNT(_n) (GDM_BASE(_n) + 0x168)
197 -#define REG_FE_GDM_RX_ETH_BC_CNT(_n) (GDM_BASE(_n) + 0x16c)
198 -#define REG_FE_GDM_RX_ETH_MC_CNT(_n) (GDM_BASE(_n) + 0x170)
199 -#define REG_FE_GDM_RX_ETH_CRC_ERR_CNT(_n) (GDM_BASE(_n) + 0x174)
200 -#define REG_FE_GDM_RX_ETH_FRAG_CNT(_n) (GDM_BASE(_n) + 0x178)
201 -#define REG_FE_GDM_RX_ETH_JABBER_CNT(_n) (GDM_BASE(_n) + 0x17c)
202 -#define REG_FE_GDM_RX_ETH_RUNT_CNT(_n) (GDM_BASE(_n) + 0x180)
203 -#define REG_FE_GDM_RX_ETH_LONG_CNT(_n) (GDM_BASE(_n) + 0x184)
204 -#define REG_FE_GDM_RX_ETH_E64_CNT_L(_n) (GDM_BASE(_n) + 0x188)
205 -#define REG_FE_GDM_RX_ETH_L64_CNT_L(_n) (GDM_BASE(_n) + 0x18c)
206 -#define REG_FE_GDM_RX_ETH_L127_CNT_L(_n) (GDM_BASE(_n) + 0x190)
207 -#define REG_FE_GDM_RX_ETH_L255_CNT_L(_n) (GDM_BASE(_n) + 0x194)
208 -#define REG_FE_GDM_RX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x198)
209 -#define REG_FE_GDM_RX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x19c)
210 -
211 -#define REG_PPE1_TB_HASH_CFG (PPE1_BASE + 0x250)
212 -#define PPE1_SRAM_TABLE_EN_MASK BIT(0)
213 -#define PPE1_SRAM_HASH1_EN_MASK BIT(8)
214 -#define PPE1_DRAM_TABLE_EN_MASK BIT(16)
215 -#define PPE1_DRAM_HASH1_EN_MASK BIT(24)
216 -
217 -#define REG_FE_GDM_TX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x280)
218 -#define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x284)
219 -#define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x288)
220 -#define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x28c)
221 -
222 -#define REG_FE_GDM_RX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x290)
223 -#define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x294)
224 -#define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x298)
225 -#define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x29c)
226 -#define REG_FE_GDM_TX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2b8)
227 -#define REG_FE_GDM_TX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2bc)
228 -#define REG_FE_GDM_TX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2c0)
229 -#define REG_FE_GDM_TX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2c4)
230 -#define REG_FE_GDM_TX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2c8)
231 -#define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2cc)
232 -#define REG_FE_GDM_RX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2e8)
233 -#define REG_FE_GDM_RX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2ec)
234 -#define REG_FE_GDM_RX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2f0)
235 -#define REG_FE_GDM_RX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2f4)
236 -#define REG_FE_GDM_RX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2f8)
237 -#define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2fc)
238 -
239 -#define REG_GDM2_CHN_RLS (GDM2_BASE + 0x20)
240 -#define MBI_RX_AGE_SEL_MASK GENMASK(26, 25)
241 -#define MBI_TX_AGE_SEL_MASK GENMASK(18, 17)
242 -
243 -#define REG_GDM3_FWD_CFG GDM3_BASE
244 -#define GDM3_PAD_EN_MASK BIT(28)
245 -
246 -#define REG_GDM4_FWD_CFG GDM4_BASE
247 -#define GDM4_PAD_EN_MASK BIT(28)
248 -#define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8)
249 -
250 -#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c)
251 -#define GDM4_SPORT_OFF2_MASK GENMASK(19, 16)
252 -#define GDM4_SPORT_OFF1_MASK GENMASK(15, 12)
253 -#define GDM4_SPORT_OFF0_MASK GENMASK(11, 8)
254 -
255 -#define REG_IP_FRAG_FP 0x2010
256 -#define IP_ASSEMBLE_PORT_MASK GENMASK(24, 21)
257 -#define IP_ASSEMBLE_NBQ_MASK GENMASK(20, 16)
258 -#define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)
259 -#define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)
260 -
261 -#define REG_MC_VLAN_EN 0x2100
262 -#define MC_VLAN_EN_MASK BIT(0)
263 -
264 -#define REG_MC_VLAN_CFG 0x2104
265 -#define MC_VLAN_CFG_CMD_DONE_MASK BIT(31)
266 -#define MC_VLAN_CFG_TABLE_ID_MASK GENMASK(21, 16)
267 -#define MC_VLAN_CFG_PORT_ID_MASK GENMASK(11, 8)
268 -#define MC_VLAN_CFG_TABLE_SEL_MASK BIT(4)
269 -#define MC_VLAN_CFG_RW_MASK BIT(0)
270 -
271 -#define REG_MC_VLAN_DATA 0x2108
272 -
273 -#define REG_CDM5_RX_OQ1_DROP_CNT 0x29d4
274 -
275 -/* QDMA */
276 -#define REG_QDMA_GLOBAL_CFG 0x0004
277 -#define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31)
278 -#define GLOBAL_CFG_DMA_PREFERENCE_MASK GENMASK(30, 29)
279 -#define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28)
280 -#define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27)
281 -#define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26)
282 -#define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25)
283 -#define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24)
284 -#define GLOBAL_CFG_RESET_MASK BIT(23)
285 -#define GLOBAL_CFG_RESET_DONE_MASK BIT(22)
286 -#define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21)
287 -#define GLOBAL_CFG_IRQ1_EN_MASK BIT(20)
288 -#define GLOBAL_CFG_IRQ0_EN_MASK BIT(19)
289 -#define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18)
290 -#define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17)
291 -#define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16)
292 -#define GLOBAL_CFG_LPBK_RXQ_SEL_MASK GENMASK(13, 8)
293 -#define GLOBAL_CFG_CHECK_DONE_MASK BIT(7)
294 -#define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6)
295 -#define GLOBAL_CFG_MAX_ISSUE_NUM_MASK GENMASK(5, 4)
296 -#define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3)
297 -#define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2)
298 -#define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1)
299 -#define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0)
300 -
301 -#define REG_FWD_DSCP_BASE 0x0010
302 -#define REG_FWD_BUF_BASE 0x0014
303 -
304 -#define REG_HW_FWD_DSCP_CFG 0x0018
305 -#define HW_FWD_DSCP_PAYLOAD_SIZE_MASK GENMASK(29, 28)
306 -#define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16)
307 -#define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK GENMASK(15, 0)
308 -
309 -#define REG_INT_STATUS(_n) \
310 - (((_n) == 4) ? 0x0730 : \
311 - ((_n) == 3) ? 0x0724 : \
312 - ((_n) == 2) ? 0x0720 : \
313 - ((_n) == 1) ? 0x0024 : 0x0020)
314 -
315 -#define REG_INT_ENABLE(_n) \
316 - (((_n) == 4) ? 0x0750 : \
317 - ((_n) == 3) ? 0x0744 : \
318 - ((_n) == 2) ? 0x0740 : \
319 - ((_n) == 1) ? 0x002c : 0x0028)
320 -
321 -/* QDMA_CSR_INT_ENABLE1 */
322 -#define RX15_COHERENT_INT_MASK BIT(31)
323 -#define RX14_COHERENT_INT_MASK BIT(30)
324 -#define RX13_COHERENT_INT_MASK BIT(29)
325 -#define RX12_COHERENT_INT_MASK BIT(28)
326 -#define RX11_COHERENT_INT_MASK BIT(27)
327 -#define RX10_COHERENT_INT_MASK BIT(26)
328 -#define RX9_COHERENT_INT_MASK BIT(25)
329 -#define RX8_COHERENT_INT_MASK BIT(24)
330 -#define RX7_COHERENT_INT_MASK BIT(23)
331 -#define RX6_COHERENT_INT_MASK BIT(22)
332 -#define RX5_COHERENT_INT_MASK BIT(21)
333 -#define RX4_COHERENT_INT_MASK BIT(20)
334 -#define RX3_COHERENT_INT_MASK BIT(19)
335 -#define RX2_COHERENT_INT_MASK BIT(18)
336 -#define RX1_COHERENT_INT_MASK BIT(17)
337 -#define RX0_COHERENT_INT_MASK BIT(16)
338 -#define TX7_COHERENT_INT_MASK BIT(15)
339 -#define TX6_COHERENT_INT_MASK BIT(14)
340 -#define TX5_COHERENT_INT_MASK BIT(13)
341 -#define TX4_COHERENT_INT_MASK BIT(12)
342 -#define TX3_COHERENT_INT_MASK BIT(11)
343 -#define TX2_COHERENT_INT_MASK BIT(10)
344 -#define TX1_COHERENT_INT_MASK BIT(9)
345 -#define TX0_COHERENT_INT_MASK BIT(8)
346 -#define CNT_OVER_FLOW_INT_MASK BIT(7)
347 -#define IRQ1_FULL_INT_MASK BIT(5)
348 -#define IRQ1_INT_MASK BIT(4)
349 -#define HWFWD_DSCP_LOW_INT_MASK BIT(3)
350 -#define HWFWD_DSCP_EMPTY_INT_MASK BIT(2)
351 -#define IRQ0_FULL_INT_MASK BIT(1)
352 -#define IRQ0_INT_MASK BIT(0)
353 -
354 -#define TX_DONE_INT_MASK(_n) \
355 - ((_n) ? IRQ1_INT_MASK | IRQ1_FULL_INT_MASK \
356 - : IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
357 -
358 -#define INT_TX_MASK \
359 - (IRQ1_INT_MASK | IRQ1_FULL_INT_MASK | \
360 - IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
361 -
362 -#define INT_IDX0_MASK \
363 - (TX0_COHERENT_INT_MASK | TX1_COHERENT_INT_MASK | \
364 - TX2_COHERENT_INT_MASK | TX3_COHERENT_INT_MASK | \
365 - TX4_COHERENT_INT_MASK | TX5_COHERENT_INT_MASK | \
366 - TX6_COHERENT_INT_MASK | TX7_COHERENT_INT_MASK | \
367 - RX0_COHERENT_INT_MASK | RX1_COHERENT_INT_MASK | \
368 - RX2_COHERENT_INT_MASK | RX3_COHERENT_INT_MASK | \
369 - RX4_COHERENT_INT_MASK | RX7_COHERENT_INT_MASK | \
370 - RX8_COHERENT_INT_MASK | RX9_COHERENT_INT_MASK | \
371 - RX15_COHERENT_INT_MASK | INT_TX_MASK)
372 -
373 -/* QDMA_CSR_INT_ENABLE2 */
374 -#define RX15_NO_CPU_DSCP_INT_MASK BIT(31)
375 -#define RX14_NO_CPU_DSCP_INT_MASK BIT(30)
376 -#define RX13_NO_CPU_DSCP_INT_MASK BIT(29)
377 -#define RX12_NO_CPU_DSCP_INT_MASK BIT(28)
378 -#define RX11_NO_CPU_DSCP_INT_MASK BIT(27)
379 -#define RX10_NO_CPU_DSCP_INT_MASK BIT(26)
380 -#define RX9_NO_CPU_DSCP_INT_MASK BIT(25)
381 -#define RX8_NO_CPU_DSCP_INT_MASK BIT(24)
382 -#define RX7_NO_CPU_DSCP_INT_MASK BIT(23)
383 -#define RX6_NO_CPU_DSCP_INT_MASK BIT(22)
384 -#define RX5_NO_CPU_DSCP_INT_MASK BIT(21)
385 -#define RX4_NO_CPU_DSCP_INT_MASK BIT(20)
386 -#define RX3_NO_CPU_DSCP_INT_MASK BIT(19)
387 -#define RX2_NO_CPU_DSCP_INT_MASK BIT(18)
388 -#define RX1_NO_CPU_DSCP_INT_MASK BIT(17)
389 -#define RX0_NO_CPU_DSCP_INT_MASK BIT(16)
390 -#define RX15_DONE_INT_MASK BIT(15)
391 -#define RX14_DONE_INT_MASK BIT(14)
392 -#define RX13_DONE_INT_MASK BIT(13)
393 -#define RX12_DONE_INT_MASK BIT(12)
394 -#define RX11_DONE_INT_MASK BIT(11)
395 -#define RX10_DONE_INT_MASK BIT(10)
396 -#define RX9_DONE_INT_MASK BIT(9)
397 -#define RX8_DONE_INT_MASK BIT(8)
398 -#define RX7_DONE_INT_MASK BIT(7)
399 -#define RX6_DONE_INT_MASK BIT(6)
400 -#define RX5_DONE_INT_MASK BIT(5)
401 -#define RX4_DONE_INT_MASK BIT(4)
402 -#define RX3_DONE_INT_MASK BIT(3)
403 -#define RX2_DONE_INT_MASK BIT(2)
404 -#define RX1_DONE_INT_MASK BIT(1)
405 -#define RX0_DONE_INT_MASK BIT(0)
406 -
407 -#define RX_DONE_INT_MASK \
408 - (RX0_DONE_INT_MASK | RX1_DONE_INT_MASK | \
409 - RX2_DONE_INT_MASK | RX3_DONE_INT_MASK | \
410 - RX4_DONE_INT_MASK | RX7_DONE_INT_MASK | \
411 - RX8_DONE_INT_MASK | RX9_DONE_INT_MASK | \
412 - RX15_DONE_INT_MASK)
413 -#define INT_IDX1_MASK \
414 - (RX_DONE_INT_MASK | \
415 - RX0_NO_CPU_DSCP_INT_MASK | RX1_NO_CPU_DSCP_INT_MASK | \
416 - RX2_NO_CPU_DSCP_INT_MASK | RX3_NO_CPU_DSCP_INT_MASK | \
417 - RX4_NO_CPU_DSCP_INT_MASK | RX7_NO_CPU_DSCP_INT_MASK | \
418 - RX8_NO_CPU_DSCP_INT_MASK | RX9_NO_CPU_DSCP_INT_MASK | \
419 - RX15_NO_CPU_DSCP_INT_MASK)
420 -
421 -/* QDMA_CSR_INT_ENABLE5 */
422 -#define TX31_COHERENT_INT_MASK BIT(31)
423 -#define TX30_COHERENT_INT_MASK BIT(30)
424 -#define TX29_COHERENT_INT_MASK BIT(29)
425 -#define TX28_COHERENT_INT_MASK BIT(28)
426 -#define TX27_COHERENT_INT_MASK BIT(27)
427 -#define TX26_COHERENT_INT_MASK BIT(26)
428 -#define TX25_COHERENT_INT_MASK BIT(25)
429 -#define TX24_COHERENT_INT_MASK BIT(24)
430 -#define TX23_COHERENT_INT_MASK BIT(23)
431 -#define TX22_COHERENT_INT_MASK BIT(22)
432 -#define TX21_COHERENT_INT_MASK BIT(21)
433 -#define TX20_COHERENT_INT_MASK BIT(20)
434 -#define TX19_COHERENT_INT_MASK BIT(19)
435 -#define TX18_COHERENT_INT_MASK BIT(18)
436 -#define TX17_COHERENT_INT_MASK BIT(17)
437 -#define TX16_COHERENT_INT_MASK BIT(16)
438 -#define TX15_COHERENT_INT_MASK BIT(15)
439 -#define TX14_COHERENT_INT_MASK BIT(14)
440 -#define TX13_COHERENT_INT_MASK BIT(13)
441 -#define TX12_COHERENT_INT_MASK BIT(12)
442 -#define TX11_COHERENT_INT_MASK BIT(11)
443 -#define TX10_COHERENT_INT_MASK BIT(10)
444 -#define TX9_COHERENT_INT_MASK BIT(9)
445 -#define TX8_COHERENT_INT_MASK BIT(8)
446 -
447 -#define INT_IDX4_MASK \
448 - (TX8_COHERENT_INT_MASK | TX9_COHERENT_INT_MASK | \
449 - TX10_COHERENT_INT_MASK | TX11_COHERENT_INT_MASK | \
450 - TX12_COHERENT_INT_MASK | TX13_COHERENT_INT_MASK | \
451 - TX14_COHERENT_INT_MASK | TX15_COHERENT_INT_MASK | \
452 - TX16_COHERENT_INT_MASK | TX17_COHERENT_INT_MASK | \
453 - TX18_COHERENT_INT_MASK | TX19_COHERENT_INT_MASK | \
454 - TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK | \
455 - TX22_COHERENT_INT_MASK | TX23_COHERENT_INT_MASK | \
456 - TX24_COHERENT_INT_MASK | TX25_COHERENT_INT_MASK | \
457 - TX26_COHERENT_INT_MASK | TX27_COHERENT_INT_MASK | \
458 - TX28_COHERENT_INT_MASK | TX29_COHERENT_INT_MASK | \
459 - TX30_COHERENT_INT_MASK | TX31_COHERENT_INT_MASK)
460 -
461 -#define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050)
462 -
463 -#define REG_TX_IRQ_CFG(_n) ((_n) ? 0x004c : 0x0054)
464 -#define TX_IRQ_THR_MASK GENMASK(27, 16)
465 -#define TX_IRQ_DEPTH_MASK GENMASK(11, 0)
466 -
467 -#define REG_IRQ_CLEAR_LEN(_n) ((_n) ? 0x0064 : 0x0058)
468 -#define IRQ_CLEAR_LEN_MASK GENMASK(7, 0)
469 -
470 -#define REG_IRQ_STATUS(_n) ((_n) ? 0x0068 : 0x005c)
471 -#define IRQ_ENTRY_LEN_MASK GENMASK(27, 16)
472 -#define IRQ_HEAD_IDX_MASK GENMASK(11, 0)
473 -
474 -#define REG_TX_RING_BASE(_n) \
475 - (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5))
476 -
477 -#define REG_TX_RING_BLOCKING(_n) \
478 - (((_n) < 8) ? 0x0104 + ((_n) << 5) : 0x0b04 + (((_n) - 8) << 5))
479 -
480 -#define TX_RING_IRQ_BLOCKING_MAP_MASK BIT(6)
481 -#define TX_RING_IRQ_BLOCKING_CFG_MASK BIT(4)
482 -#define TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK BIT(2)
483 -#define TX_RING_IRQ_BLOCKING_MAX_TH_TXRING_EN_MASK BIT(1)
484 -#define TX_RING_IRQ_BLOCKING_MIN_TH_TXRING_EN_MASK BIT(0)
485 -
486 -#define REG_TX_CPU_IDX(_n) \
487 - (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5))
488 -
489 -#define TX_RING_CPU_IDX_MASK GENMASK(15, 0)
490 -
491 -#define REG_TX_DMA_IDX(_n) \
492 - (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5))
493 -
494 -#define TX_RING_DMA_IDX_MASK GENMASK(15, 0)
495 -
496 -#define IRQ_RING_IDX_MASK GENMASK(20, 16)
497 -#define IRQ_DESC_IDX_MASK GENMASK(15, 0)
498 -
499 -#define REG_RX_RING_BASE(_n) \
500 - (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5))
501 -
502 -#define REG_RX_RING_SIZE(_n) \
503 - (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5))
504 -
505 -#define RX_RING_THR_MASK GENMASK(31, 16)
506 -#define RX_RING_SIZE_MASK GENMASK(15, 0)
507 -
508 -#define REG_RX_CPU_IDX(_n) \
509 - (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5))
510 -
511 -#define RX_RING_CPU_IDX_MASK GENMASK(15, 0)
512 -
513 -#define REG_RX_DMA_IDX(_n) \
514 - (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5))
515 -
516 -#define REG_RX_DELAY_INT_IDX(_n) \
517 - (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
518 -
519 -#define RX_DELAY_INT_MASK GENMASK(15, 0)
520 -
521 -#define RX_RING_DMA_IDX_MASK GENMASK(15, 0)
522 -
523 -#define REG_INGRESS_TRTCM_CFG 0x0070
524 -#define INGRESS_TRTCM_EN_MASK BIT(31)
525 -#define INGRESS_TRTCM_MODE_MASK BIT(30)
526 -#define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
527 -#define INGRESS_FAST_TICK_MASK GENMASK(15, 0)
528 -
529 -#define REG_QUEUE_CLOSE_CFG(_n) (0x00a0 + ((_n) & 0xfc))
530 -#define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) BIT((_m) + (((_n) & 0x3) << 3))
531 -
532 -#define REG_TXQ_DIS_CFG_BASE(_n) ((_n) ? 0x20a0 : 0x00a0)
533 -#define REG_TXQ_DIS_CFG(_n, _m) (REG_TXQ_DIS_CFG_BASE((_n)) + (_m) << 2)
534 -
535 -#define REG_CNTR_CFG(_n) (0x0400 + ((_n) << 3))
536 -#define CNTR_EN_MASK BIT(31)
537 -#define CNTR_ALL_CHAN_EN_MASK BIT(30)
538 -#define CNTR_ALL_QUEUE_EN_MASK BIT(29)
539 -#define CNTR_ALL_DSCP_RING_EN_MASK BIT(28)
540 -#define CNTR_SRC_MASK GENMASK(27, 24)
541 -#define CNTR_DSCP_RING_MASK GENMASK(20, 16)
542 -#define CNTR_CHAN_MASK GENMASK(7, 3)
543 -#define CNTR_QUEUE_MASK GENMASK(2, 0)
544 -
545 -#define REG_CNTR_VAL(_n) (0x0404 + ((_n) << 3))
546 -
547 -#define REG_LMGR_INIT_CFG 0x1000
548 -#define LMGR_INIT_START BIT(31)
549 -#define LMGR_SRAM_MODE_MASK BIT(30)
550 -#define HW_FWD_PKTSIZE_OVERHEAD_MASK GENMASK(27, 20)
551 -#define HW_FWD_DESC_NUM_MASK GENMASK(16, 0)
552 -
553 -#define REG_FWD_DSCP_LOW_THR 0x1004
554 -#define FWD_DSCP_LOW_THR_MASK GENMASK(17, 0)
555 -
556 -#define REG_EGRESS_RATE_METER_CFG 0x100c
557 -#define EGRESS_RATE_METER_EN_MASK BIT(31)
558 -#define EGRESS_RATE_METER_EQ_RATE_EN_MASK BIT(17)
559 -#define EGRESS_RATE_METER_WINDOW_SZ_MASK GENMASK(16, 12)
560 -#define EGRESS_RATE_METER_TIMESLICE_MASK GENMASK(10, 0)
561 -
562 -#define REG_EGRESS_TRTCM_CFG 0x1010
563 -#define EGRESS_TRTCM_EN_MASK BIT(31)
564 -#define EGRESS_TRTCM_MODE_MASK BIT(30)
565 -#define EGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
566 -#define EGRESS_FAST_TICK_MASK GENMASK(15, 0)
567 -
568 -#define TRTCM_PARAM_RW_MASK BIT(31)
569 -#define TRTCM_PARAM_RW_DONE_MASK BIT(30)
570 -#define TRTCM_PARAM_TYPE_MASK GENMASK(29, 28)
571 -#define TRTCM_METER_GROUP_MASK GENMASK(27, 26)
572 -#define TRTCM_PARAM_INDEX_MASK GENMASK(23, 17)
573 -#define TRTCM_PARAM_RATE_TYPE_MASK BIT(16)
574 -
575 -#define REG_TRTCM_CFG_PARAM(_n) ((_n) + 0x4)
576 -#define REG_TRTCM_DATA_LOW(_n) ((_n) + 0x8)
577 -#define REG_TRTCM_DATA_HIGH(_n) ((_n) + 0xc)
578 -
579 -#define REG_TXWRR_MODE_CFG 0x1020
580 -#define TWRR_WEIGHT_SCALE_MASK BIT(31)
581 -#define TWRR_WEIGHT_BASE_MASK BIT(3)
582 -
583 -#define REG_TXWRR_WEIGHT_CFG 0x1024
584 -#define TWRR_RW_CMD_MASK BIT(31)
585 -#define TWRR_RW_CMD_DONE BIT(30)
586 -#define TWRR_CHAN_IDX_MASK GENMASK(23, 19)
587 -#define TWRR_QUEUE_IDX_MASK GENMASK(18, 16)
588 -#define TWRR_VALUE_MASK GENMASK(15, 0)
589 -
590 -#define REG_PSE_BUF_USAGE_CFG 0x1028
591 -#define PSE_BUF_ESTIMATE_EN_MASK BIT(29)
592 -
593 -#define REG_CHAN_QOS_MODE(_n) (0x1040 + ((_n) << 2))
594 -#define CHAN_QOS_MODE_MASK(_n) GENMASK(2 + ((_n) << 2), (_n) << 2)
595 -
596 -#define REG_GLB_TRTCM_CFG 0x1080
597 -#define GLB_TRTCM_EN_MASK BIT(31)
598 -#define GLB_TRTCM_MODE_MASK BIT(30)
599 -#define GLB_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
600 -#define GLB_FAST_TICK_MASK GENMASK(15, 0)
601 -
602 -#define REG_TXQ_CNGST_CFG 0x10a0
603 -#define TXQ_CNGST_DROP_EN BIT(31)
604 -#define TXQ_CNGST_DEI_DROP_EN BIT(30)
605 -
606 -#define REG_SLA_TRTCM_CFG 0x1150
607 -#define SLA_TRTCM_EN_MASK BIT(31)
608 -#define SLA_TRTCM_MODE_MASK BIT(30)
609 -#define SLA_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
610 -#define SLA_FAST_TICK_MASK GENMASK(15, 0)
611 -
612 -/* CTRL */
613 -#define QDMA_DESC_DONE_MASK BIT(31)
614 -#define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */
615 -#define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */
616 -#define QDMA_DESC_DEI_MASK BIT(25)
617 -#define QDMA_DESC_NO_DROP_MASK BIT(24)
618 -#define QDMA_DESC_LEN_MASK GENMASK(15, 0)
619 -/* DATA */
620 -#define QDMA_DESC_NEXT_ID_MASK GENMASK(15, 0)
621 -/* TX MSG0 */
622 -#define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30)
623 -#define QDMA_ETH_TXMSG_SP_TAG_MASK GENMASK(29, 14)
624 -#define QDMA_ETH_TXMSG_ICO_MASK BIT(13)
625 -#define QDMA_ETH_TXMSG_UCO_MASK BIT(12)
626 -#define QDMA_ETH_TXMSG_TCO_MASK BIT(11)
627 -#define QDMA_ETH_TXMSG_TSO_MASK BIT(10)
628 -#define QDMA_ETH_TXMSG_FAST_MASK BIT(9)
629 -#define QDMA_ETH_TXMSG_OAM_MASK BIT(8)
630 -#define QDMA_ETH_TXMSG_CHAN_MASK GENMASK(7, 3)
631 -#define QDMA_ETH_TXMSG_QUEUE_MASK GENMASK(2, 0)
632 -/* TX MSG1 */
633 -#define QDMA_ETH_TXMSG_NO_DROP BIT(31)
634 -#define QDMA_ETH_TXMSG_METER_MASK GENMASK(30, 24) /* 0x7f no meters */
635 -#define QDMA_ETH_TXMSG_FPORT_MASK GENMASK(23, 20)
636 -#define QDMA_ETH_TXMSG_NBOQ_MASK GENMASK(19, 15)
637 -#define QDMA_ETH_TXMSG_HWF_MASK BIT(14)
638 -#define QDMA_ETH_TXMSG_HOP_MASK BIT(13)
639 -#define QDMA_ETH_TXMSG_PTP_MASK BIT(12)
640 -#define QDMA_ETH_TXMSG_ACNT_G1_MASK GENMASK(10, 6) /* 0x1f do not count */
641 -#define QDMA_ETH_TXMSG_ACNT_G0_MASK GENMASK(5, 0) /* 0x3f do not count */
642 -
643 -/* RX MSG1 */
644 -#define QDMA_ETH_RXMSG_DEI_MASK BIT(31)
645 -#define QDMA_ETH_RXMSG_IP6_MASK BIT(30)
646 -#define QDMA_ETH_RXMSG_IP4_MASK BIT(29)
647 -#define QDMA_ETH_RXMSG_IP4F_MASK BIT(28)
648 -#define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27)
649 -#define QDMA_ETH_RXMSG_L4F_MASK BIT(26)
650 -#define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21)
651 -#define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16)
652 -#define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0)
653 -
654 -struct airoha_qdma_desc {
655 - __le32 rsv;
656 - __le32 ctrl;
657 - __le32 addr;
658 - __le32 data;
659 - __le32 msg0;
660 - __le32 msg1;
661 - __le32 msg2;
662 - __le32 msg3;
663 -};
664 -
665 -/* CTRL0 */
666 -#define QDMA_FWD_DESC_CTX_MASK BIT(31)
667 -#define QDMA_FWD_DESC_RING_MASK GENMASK(30, 28)
668 -#define QDMA_FWD_DESC_IDX_MASK GENMASK(27, 16)
669 -#define QDMA_FWD_DESC_LEN_MASK GENMASK(15, 0)
670 -/* CTRL1 */
671 -#define QDMA_FWD_DESC_FIRST_IDX_MASK GENMASK(15, 0)
672 -/* CTRL2 */
673 -#define QDMA_FWD_DESC_MORE_PKT_NUM_MASK GENMASK(2, 0)
674 -
675 -struct airoha_qdma_fwd_desc {
676 - __le32 addr;
677 - __le32 ctrl0;
678 - __le32 ctrl1;
679 - __le32 ctrl2;
680 - __le32 msg0;
681 - __le32 msg1;
682 - __le32 rsv0;
683 - __le32 rsv1;
684 -};
685 -
686 u32 airoha_rr(void __iomem *base, u32 offset)
687 {
688 return readl(base + offset);
689 --- /dev/null
690 +++ b/drivers/net/ethernet/airoha/airoha_regs.h
691 @@ -0,0 +1,670 @@
692 +/* SPDX-License-Identifier: GPL-2.0-only */
693 +/*
694 + * Copyright (c) 2024 AIROHA Inc
695 + * Author: Lorenzo Bianconi <lorenzo@kernel.org>
696 + */
697 +
698 +#ifndef AIROHA_REGS_H
699 +#define AIROHA_REGS_H
700 +
701 +#include <linux/types.h>
702 +
703 +/* FE */
704 +#define PSE_BASE 0x0100
705 +#define CSR_IFC_BASE 0x0200
706 +#define CDM1_BASE 0x0400
707 +#define GDM1_BASE 0x0500
708 +#define PPE1_BASE 0x0c00
709 +
710 +#define CDM2_BASE 0x1400
711 +#define GDM2_BASE 0x1500
712 +
713 +#define GDM3_BASE 0x1100
714 +#define GDM4_BASE 0x2500
715 +
716 +#define GDM_BASE(_n) \
717 + ((_n) == 4 ? GDM4_BASE : \
718 + (_n) == 3 ? GDM3_BASE : \
719 + (_n) == 2 ? GDM2_BASE : GDM1_BASE)
720 +
721 +#define REG_FE_DMA_GLO_CFG 0x0000
722 +#define FE_DMA_GLO_L2_SPACE_MASK GENMASK(7, 4)
723 +#define FE_DMA_GLO_PG_SZ_MASK BIT(3)
724 +
725 +#define REG_FE_RST_GLO_CFG 0x0004
726 +#define FE_RST_GDM4_MBI_ARB_MASK BIT(3)
727 +#define FE_RST_GDM3_MBI_ARB_MASK BIT(2)
728 +#define FE_RST_CORE_MASK BIT(0)
729 +
730 +#define REG_FE_WAN_MAC_H 0x0030
731 +#define REG_FE_LAN_MAC_H 0x0040
732 +
733 +#define REG_FE_MAC_LMIN(_n) ((_n) + 0x04)
734 +#define REG_FE_MAC_LMAX(_n) ((_n) + 0x08)
735 +
736 +#define REG_FE_CDM1_OQ_MAP0 0x0050
737 +#define REG_FE_CDM1_OQ_MAP1 0x0054
738 +#define REG_FE_CDM1_OQ_MAP2 0x0058
739 +#define REG_FE_CDM1_OQ_MAP3 0x005c
740 +
741 +#define REG_FE_PCE_CFG 0x0070
742 +#define PCE_DPI_EN_MASK BIT(2)
743 +#define PCE_KA_EN_MASK BIT(1)
744 +#define PCE_MC_EN_MASK BIT(0)
745 +
746 +#define REG_FE_PSE_QUEUE_CFG_WR 0x0080
747 +#define PSE_CFG_PORT_ID_MASK GENMASK(27, 24)
748 +#define PSE_CFG_QUEUE_ID_MASK GENMASK(20, 16)
749 +#define PSE_CFG_WR_EN_MASK BIT(8)
750 +#define PSE_CFG_OQRSV_SEL_MASK BIT(0)
751 +
752 +#define REG_FE_PSE_QUEUE_CFG_VAL 0x0084
753 +#define PSE_CFG_OQ_RSV_MASK GENMASK(13, 0)
754 +
755 +#define PSE_FQ_CFG 0x008c
756 +#define PSE_FQ_LIMIT_MASK GENMASK(14, 0)
757 +
758 +#define REG_FE_PSE_BUF_SET 0x0090
759 +#define PSE_SHARE_USED_LTHD_MASK GENMASK(31, 16)
760 +#define PSE_ALLRSV_MASK GENMASK(14, 0)
761 +
762 +#define REG_PSE_SHARE_USED_THD 0x0094
763 +#define PSE_SHARE_USED_MTHD_MASK GENMASK(31, 16)
764 +#define PSE_SHARE_USED_HTHD_MASK GENMASK(15, 0)
765 +
766 +#define REG_GDM_MISC_CFG 0x0148
767 +#define GDM2_RDM_ACK_WAIT_PREF_MASK BIT(9)
768 +#define GDM2_CHN_VLD_MODE_MASK BIT(5)
769 +
770 +#define REG_FE_CSR_IFC_CFG CSR_IFC_BASE
771 +#define FE_IFC_EN_MASK BIT(0)
772 +
773 +#define REG_FE_VIP_PORT_EN 0x01f0
774 +#define REG_FE_IFC_PORT_EN 0x01f4
775 +
776 +#define REG_PSE_IQ_REV1 (PSE_BASE + 0x08)
777 +#define PSE_IQ_RES1_P2_MASK GENMASK(23, 16)
778 +
779 +#define REG_PSE_IQ_REV2 (PSE_BASE + 0x0c)
780 +#define PSE_IQ_RES2_P5_MASK GENMASK(15, 8)
781 +#define PSE_IQ_RES2_P4_MASK GENMASK(7, 0)
782 +
783 +#define REG_FE_VIP_EN(_n) (0x0300 + ((_n) << 3))
784 +#define PATN_FCPU_EN_MASK BIT(7)
785 +#define PATN_SWP_EN_MASK BIT(6)
786 +#define PATN_DP_EN_MASK BIT(5)
787 +#define PATN_SP_EN_MASK BIT(4)
788 +#define PATN_TYPE_MASK GENMASK(3, 1)
789 +#define PATN_EN_MASK BIT(0)
790 +
791 +#define REG_FE_VIP_PATN(_n) (0x0304 + ((_n) << 3))
792 +#define PATN_DP_MASK GENMASK(31, 16)
793 +#define PATN_SP_MASK GENMASK(15, 0)
794 +
795 +#define REG_CDM1_VLAN_CTRL CDM1_BASE
796 +#define CDM1_VLAN_MASK GENMASK(31, 16)
797 +
798 +#define REG_CDM1_FWD_CFG (CDM1_BASE + 0x08)
799 +#define CDM1_VIP_QSEL_MASK GENMASK(24, 20)
800 +
801 +#define REG_CDM1_CRSN_QSEL(_n) (CDM1_BASE + 0x10 + ((_n) << 2))
802 +#define CDM1_CRSN_QSEL_REASON_MASK(_n) \
803 + GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3))
804 +
805 +#define REG_CDM2_FWD_CFG (CDM2_BASE + 0x08)
806 +#define CDM2_OAM_QSEL_MASK GENMASK(31, 27)
807 +#define CDM2_VIP_QSEL_MASK GENMASK(24, 20)
808 +
809 +#define REG_CDM2_CRSN_QSEL(_n) (CDM2_BASE + 0x10 + ((_n) << 2))
810 +#define CDM2_CRSN_QSEL_REASON_MASK(_n) \
811 + GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3))
812 +
813 +#define REG_GDM_FWD_CFG(_n) GDM_BASE(_n)
814 +#define GDM_DROP_CRC_ERR BIT(23)
815 +#define GDM_IP4_CKSUM BIT(22)
816 +#define GDM_TCP_CKSUM BIT(21)
817 +#define GDM_UDP_CKSUM BIT(20)
818 +#define GDM_UCFQ_MASK GENMASK(15, 12)
819 +#define GDM_BCFQ_MASK GENMASK(11, 8)
820 +#define GDM_MCFQ_MASK GENMASK(7, 4)
821 +#define GDM_OCFQ_MASK GENMASK(3, 0)
822 +
823 +#define REG_GDM_INGRESS_CFG(_n) (GDM_BASE(_n) + 0x10)
824 +#define GDM_INGRESS_FC_EN_MASK BIT(1)
825 +#define GDM_STAG_EN_MASK BIT(0)
826 +
827 +#define REG_GDM_LEN_CFG(_n) (GDM_BASE(_n) + 0x14)
828 +#define GDM_SHORT_LEN_MASK GENMASK(13, 0)
829 +#define GDM_LONG_LEN_MASK GENMASK(29, 16)
830 +
831 +#define REG_FE_CPORT_CFG (GDM1_BASE + 0x40)
832 +#define FE_CPORT_PAD BIT(26)
833 +#define FE_CPORT_PORT_XFC_MASK BIT(25)
834 +#define FE_CPORT_QUEUE_XFC_MASK BIT(24)
835 +
836 +#define REG_FE_GDM_MIB_CLEAR(_n) (GDM_BASE(_n) + 0xf0)
837 +#define FE_GDM_MIB_RX_CLEAR_MASK BIT(1)
838 +#define FE_GDM_MIB_TX_CLEAR_MASK BIT(0)
839 +
840 +#define REG_FE_GDM1_MIB_CFG (GDM1_BASE + 0xf4)
841 +#define FE_STRICT_RFC2819_MODE_MASK BIT(31)
842 +#define FE_GDM1_TX_MIB_SPLIT_EN_MASK BIT(17)
843 +#define FE_GDM1_RX_MIB_SPLIT_EN_MASK BIT(16)
844 +#define FE_TX_MIB_ID_MASK GENMASK(15, 8)
845 +#define FE_RX_MIB_ID_MASK GENMASK(7, 0)
846 +
847 +#define REG_FE_GDM_TX_OK_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x104)
848 +#define REG_FE_GDM_TX_OK_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x10c)
849 +#define REG_FE_GDM_TX_ETH_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x110)
850 +#define REG_FE_GDM_TX_ETH_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x114)
851 +#define REG_FE_GDM_TX_ETH_DROP_CNT(_n) (GDM_BASE(_n) + 0x118)
852 +#define REG_FE_GDM_TX_ETH_BC_CNT(_n) (GDM_BASE(_n) + 0x11c)
853 +#define REG_FE_GDM_TX_ETH_MC_CNT(_n) (GDM_BASE(_n) + 0x120)
854 +#define REG_FE_GDM_TX_ETH_RUNT_CNT(_n) (GDM_BASE(_n) + 0x124)
855 +#define REG_FE_GDM_TX_ETH_LONG_CNT(_n) (GDM_BASE(_n) + 0x128)
856 +#define REG_FE_GDM_TX_ETH_E64_CNT_L(_n) (GDM_BASE(_n) + 0x12c)
857 +#define REG_FE_GDM_TX_ETH_L64_CNT_L(_n) (GDM_BASE(_n) + 0x130)
858 +#define REG_FE_GDM_TX_ETH_L127_CNT_L(_n) (GDM_BASE(_n) + 0x134)
859 +#define REG_FE_GDM_TX_ETH_L255_CNT_L(_n) (GDM_BASE(_n) + 0x138)
860 +#define REG_FE_GDM_TX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x13c)
861 +#define REG_FE_GDM_TX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x140)
862 +
863 +#define REG_FE_GDM_RX_OK_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x148)
864 +#define REG_FE_GDM_RX_FC_DROP_CNT(_n) (GDM_BASE(_n) + 0x14c)
865 +#define REG_FE_GDM_RX_RC_DROP_CNT(_n) (GDM_BASE(_n) + 0x150)
866 +#define REG_FE_GDM_RX_OVERFLOW_DROP_CNT(_n) (GDM_BASE(_n) + 0x154)
867 +#define REG_FE_GDM_RX_ERROR_DROP_CNT(_n) (GDM_BASE(_n) + 0x158)
868 +#define REG_FE_GDM_RX_OK_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x15c)
869 +#define REG_FE_GDM_RX_ETH_PKT_CNT_L(_n) (GDM_BASE(_n) + 0x160)
870 +#define REG_FE_GDM_RX_ETH_BYTE_CNT_L(_n) (GDM_BASE(_n) + 0x164)
871 +#define REG_FE_GDM_RX_ETH_DROP_CNT(_n) (GDM_BASE(_n) + 0x168)
872 +#define REG_FE_GDM_RX_ETH_BC_CNT(_n) (GDM_BASE(_n) + 0x16c)
873 +#define REG_FE_GDM_RX_ETH_MC_CNT(_n) (GDM_BASE(_n) + 0x170)
874 +#define REG_FE_GDM_RX_ETH_CRC_ERR_CNT(_n) (GDM_BASE(_n) + 0x174)
875 +#define REG_FE_GDM_RX_ETH_FRAG_CNT(_n) (GDM_BASE(_n) + 0x178)
876 +#define REG_FE_GDM_RX_ETH_JABBER_CNT(_n) (GDM_BASE(_n) + 0x17c)
877 +#define REG_FE_GDM_RX_ETH_RUNT_CNT(_n) (GDM_BASE(_n) + 0x180)
878 +#define REG_FE_GDM_RX_ETH_LONG_CNT(_n) (GDM_BASE(_n) + 0x184)
879 +#define REG_FE_GDM_RX_ETH_E64_CNT_L(_n) (GDM_BASE(_n) + 0x188)
880 +#define REG_FE_GDM_RX_ETH_L64_CNT_L(_n) (GDM_BASE(_n) + 0x18c)
881 +#define REG_FE_GDM_RX_ETH_L127_CNT_L(_n) (GDM_BASE(_n) + 0x190)
882 +#define REG_FE_GDM_RX_ETH_L255_CNT_L(_n) (GDM_BASE(_n) + 0x194)
883 +#define REG_FE_GDM_RX_ETH_L511_CNT_L(_n) (GDM_BASE(_n) + 0x198)
884 +#define REG_FE_GDM_RX_ETH_L1023_CNT_L(_n) (GDM_BASE(_n) + 0x19c)
885 +
886 +#define REG_PPE1_TB_HASH_CFG (PPE1_BASE + 0x250)
887 +#define PPE1_SRAM_TABLE_EN_MASK BIT(0)
888 +#define PPE1_SRAM_HASH1_EN_MASK BIT(8)
889 +#define PPE1_DRAM_TABLE_EN_MASK BIT(16)
890 +#define PPE1_DRAM_HASH1_EN_MASK BIT(24)
891 +
892 +#define REG_FE_GDM_TX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x280)
893 +#define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x284)
894 +#define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x288)
895 +#define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x28c)
896 +
897 +#define REG_FE_GDM_RX_OK_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x290)
898 +#define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x294)
899 +#define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n) (GDM_BASE(_n) + 0x298)
900 +#define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n) (GDM_BASE(_n) + 0x29c)
901 +#define REG_FE_GDM_TX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2b8)
902 +#define REG_FE_GDM_TX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2bc)
903 +#define REG_FE_GDM_TX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2c0)
904 +#define REG_FE_GDM_TX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2c4)
905 +#define REG_FE_GDM_TX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2c8)
906 +#define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2cc)
907 +#define REG_FE_GDM_RX_ETH_E64_CNT_H(_n) (GDM_BASE(_n) + 0x2e8)
908 +#define REG_FE_GDM_RX_ETH_L64_CNT_H(_n) (GDM_BASE(_n) + 0x2ec)
909 +#define REG_FE_GDM_RX_ETH_L127_CNT_H(_n) (GDM_BASE(_n) + 0x2f0)
910 +#define REG_FE_GDM_RX_ETH_L255_CNT_H(_n) (GDM_BASE(_n) + 0x2f4)
911 +#define REG_FE_GDM_RX_ETH_L511_CNT_H(_n) (GDM_BASE(_n) + 0x2f8)
912 +#define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n) (GDM_BASE(_n) + 0x2fc)
913 +
914 +#define REG_GDM2_CHN_RLS (GDM2_BASE + 0x20)
915 +#define MBI_RX_AGE_SEL_MASK GENMASK(26, 25)
916 +#define MBI_TX_AGE_SEL_MASK GENMASK(18, 17)
917 +
918 +#define REG_GDM3_FWD_CFG GDM3_BASE
919 +#define GDM3_PAD_EN_MASK BIT(28)
920 +
921 +#define REG_GDM4_FWD_CFG GDM4_BASE
922 +#define GDM4_PAD_EN_MASK BIT(28)
923 +#define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8)
924 +
925 +#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c)
926 +#define GDM4_SPORT_OFF2_MASK GENMASK(19, 16)
927 +#define GDM4_SPORT_OFF1_MASK GENMASK(15, 12)
928 +#define GDM4_SPORT_OFF0_MASK GENMASK(11, 8)
929 +
930 +#define REG_IP_FRAG_FP 0x2010
931 +#define IP_ASSEMBLE_PORT_MASK GENMASK(24, 21)
932 +#define IP_ASSEMBLE_NBQ_MASK GENMASK(20, 16)
933 +#define IP_FRAGMENT_PORT_MASK GENMASK(8, 5)
934 +#define IP_FRAGMENT_NBQ_MASK GENMASK(4, 0)
935 +
936 +#define REG_MC_VLAN_EN 0x2100
937 +#define MC_VLAN_EN_MASK BIT(0)
938 +
939 +#define REG_MC_VLAN_CFG 0x2104
940 +#define MC_VLAN_CFG_CMD_DONE_MASK BIT(31)
941 +#define MC_VLAN_CFG_TABLE_ID_MASK GENMASK(21, 16)
942 +#define MC_VLAN_CFG_PORT_ID_MASK GENMASK(11, 8)
943 +#define MC_VLAN_CFG_TABLE_SEL_MASK BIT(4)
944 +#define MC_VLAN_CFG_RW_MASK BIT(0)
945 +
946 +#define REG_MC_VLAN_DATA 0x2108
947 +
948 +#define REG_CDM5_RX_OQ1_DROP_CNT 0x29d4
949 +
950 +/* QDMA */
951 +#define REG_QDMA_GLOBAL_CFG 0x0004
952 +#define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31)
953 +#define GLOBAL_CFG_DMA_PREFERENCE_MASK GENMASK(30, 29)
954 +#define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28)
955 +#define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27)
956 +#define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26)
957 +#define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25)
958 +#define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24)
959 +#define GLOBAL_CFG_RESET_MASK BIT(23)
960 +#define GLOBAL_CFG_RESET_DONE_MASK BIT(22)
961 +#define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21)
962 +#define GLOBAL_CFG_IRQ1_EN_MASK BIT(20)
963 +#define GLOBAL_CFG_IRQ0_EN_MASK BIT(19)
964 +#define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18)
965 +#define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17)
966 +#define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16)
967 +#define GLOBAL_CFG_LPBK_RXQ_SEL_MASK GENMASK(13, 8)
968 +#define GLOBAL_CFG_CHECK_DONE_MASK BIT(7)
969 +#define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6)
970 +#define GLOBAL_CFG_MAX_ISSUE_NUM_MASK GENMASK(5, 4)
971 +#define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3)
972 +#define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2)
973 +#define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1)
974 +#define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0)
975 +
976 +#define REG_FWD_DSCP_BASE 0x0010
977 +#define REG_FWD_BUF_BASE 0x0014
978 +
979 +#define REG_HW_FWD_DSCP_CFG 0x0018
980 +#define HW_FWD_DSCP_PAYLOAD_SIZE_MASK GENMASK(29, 28)
981 +#define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16)
982 +#define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK GENMASK(15, 0)
983 +
984 +#define REG_INT_STATUS(_n) \
985 + (((_n) == 4) ? 0x0730 : \
986 + ((_n) == 3) ? 0x0724 : \
987 + ((_n) == 2) ? 0x0720 : \
988 + ((_n) == 1) ? 0x0024 : 0x0020)
989 +
990 +#define REG_INT_ENABLE(_n) \
991 + (((_n) == 4) ? 0x0750 : \
992 + ((_n) == 3) ? 0x0744 : \
993 + ((_n) == 2) ? 0x0740 : \
994 + ((_n) == 1) ? 0x002c : 0x0028)
995 +
996 +/* QDMA_CSR_INT_ENABLE1 */
997 +#define RX15_COHERENT_INT_MASK BIT(31)
998 +#define RX14_COHERENT_INT_MASK BIT(30)
999 +#define RX13_COHERENT_INT_MASK BIT(29)
1000 +#define RX12_COHERENT_INT_MASK BIT(28)
1001 +#define RX11_COHERENT_INT_MASK BIT(27)
1002 +#define RX10_COHERENT_INT_MASK BIT(26)
1003 +#define RX9_COHERENT_INT_MASK BIT(25)
1004 +#define RX8_COHERENT_INT_MASK BIT(24)
1005 +#define RX7_COHERENT_INT_MASK BIT(23)
1006 +#define RX6_COHERENT_INT_MASK BIT(22)
1007 +#define RX5_COHERENT_INT_MASK BIT(21)
1008 +#define RX4_COHERENT_INT_MASK BIT(20)
1009 +#define RX3_COHERENT_INT_MASK BIT(19)
1010 +#define RX2_COHERENT_INT_MASK BIT(18)
1011 +#define RX1_COHERENT_INT_MASK BIT(17)
1012 +#define RX0_COHERENT_INT_MASK BIT(16)
1013 +#define TX7_COHERENT_INT_MASK BIT(15)
1014 +#define TX6_COHERENT_INT_MASK BIT(14)
1015 +#define TX5_COHERENT_INT_MASK BIT(13)
1016 +#define TX4_COHERENT_INT_MASK BIT(12)
1017 +#define TX3_COHERENT_INT_MASK BIT(11)
1018 +#define TX2_COHERENT_INT_MASK BIT(10)
1019 +#define TX1_COHERENT_INT_MASK BIT(9)
1020 +#define TX0_COHERENT_INT_MASK BIT(8)
1021 +#define CNT_OVER_FLOW_INT_MASK BIT(7)
1022 +#define IRQ1_FULL_INT_MASK BIT(5)
1023 +#define IRQ1_INT_MASK BIT(4)
1024 +#define HWFWD_DSCP_LOW_INT_MASK BIT(3)
1025 +#define HWFWD_DSCP_EMPTY_INT_MASK BIT(2)
1026 +#define IRQ0_FULL_INT_MASK BIT(1)
1027 +#define IRQ0_INT_MASK BIT(0)
1028 +
1029 +#define TX_DONE_INT_MASK(_n) \
1030 + ((_n) ? IRQ1_INT_MASK | IRQ1_FULL_INT_MASK \
1031 + : IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
1032 +
1033 +#define INT_TX_MASK \
1034 + (IRQ1_INT_MASK | IRQ1_FULL_INT_MASK | \
1035 + IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
1036 +
1037 +#define INT_IDX0_MASK \
1038 + (TX0_COHERENT_INT_MASK | TX1_COHERENT_INT_MASK | \
1039 + TX2_COHERENT_INT_MASK | TX3_COHERENT_INT_MASK | \
1040 + TX4_COHERENT_INT_MASK | TX5_COHERENT_INT_MASK | \
1041 + TX6_COHERENT_INT_MASK | TX7_COHERENT_INT_MASK | \
1042 + RX0_COHERENT_INT_MASK | RX1_COHERENT_INT_MASK | \
1043 + RX2_COHERENT_INT_MASK | RX3_COHERENT_INT_MASK | \
1044 + RX4_COHERENT_INT_MASK | RX7_COHERENT_INT_MASK | \
1045 + RX8_COHERENT_INT_MASK | RX9_COHERENT_INT_MASK | \
1046 + RX15_COHERENT_INT_MASK | INT_TX_MASK)
1047 +
1048 +/* QDMA_CSR_INT_ENABLE2 */
1049 +#define RX15_NO_CPU_DSCP_INT_MASK BIT(31)
1050 +#define RX14_NO_CPU_DSCP_INT_MASK BIT(30)
1051 +#define RX13_NO_CPU_DSCP_INT_MASK BIT(29)
1052 +#define RX12_NO_CPU_DSCP_INT_MASK BIT(28)
1053 +#define RX11_NO_CPU_DSCP_INT_MASK BIT(27)
1054 +#define RX10_NO_CPU_DSCP_INT_MASK BIT(26)
1055 +#define RX9_NO_CPU_DSCP_INT_MASK BIT(25)
1056 +#define RX8_NO_CPU_DSCP_INT_MASK BIT(24)
1057 +#define RX7_NO_CPU_DSCP_INT_MASK BIT(23)
1058 +#define RX6_NO_CPU_DSCP_INT_MASK BIT(22)
1059 +#define RX5_NO_CPU_DSCP_INT_MASK BIT(21)
1060 +#define RX4_NO_CPU_DSCP_INT_MASK BIT(20)
1061 +#define RX3_NO_CPU_DSCP_INT_MASK BIT(19)
1062 +#define RX2_NO_CPU_DSCP_INT_MASK BIT(18)
1063 +#define RX1_NO_CPU_DSCP_INT_MASK BIT(17)
1064 +#define RX0_NO_CPU_DSCP_INT_MASK BIT(16)
1065 +#define RX15_DONE_INT_MASK BIT(15)
1066 +#define RX14_DONE_INT_MASK BIT(14)
1067 +#define RX13_DONE_INT_MASK BIT(13)
1068 +#define RX12_DONE_INT_MASK BIT(12)
1069 +#define RX11_DONE_INT_MASK BIT(11)
1070 +#define RX10_DONE_INT_MASK BIT(10)
1071 +#define RX9_DONE_INT_MASK BIT(9)
1072 +#define RX8_DONE_INT_MASK BIT(8)
1073 +#define RX7_DONE_INT_MASK BIT(7)
1074 +#define RX6_DONE_INT_MASK BIT(6)
1075 +#define RX5_DONE_INT_MASK BIT(5)
1076 +#define RX4_DONE_INT_MASK BIT(4)
1077 +#define RX3_DONE_INT_MASK BIT(3)
1078 +#define RX2_DONE_INT_MASK BIT(2)
1079 +#define RX1_DONE_INT_MASK BIT(1)
1080 +#define RX0_DONE_INT_MASK BIT(0)
1081 +
1082 +#define RX_DONE_INT_MASK \
1083 + (RX0_DONE_INT_MASK | RX1_DONE_INT_MASK | \
1084 + RX2_DONE_INT_MASK | RX3_DONE_INT_MASK | \
1085 + RX4_DONE_INT_MASK | RX7_DONE_INT_MASK | \
1086 + RX8_DONE_INT_MASK | RX9_DONE_INT_MASK | \
1087 + RX15_DONE_INT_MASK)
1088 +#define INT_IDX1_MASK \
1089 + (RX_DONE_INT_MASK | \
1090 + RX0_NO_CPU_DSCP_INT_MASK | RX1_NO_CPU_DSCP_INT_MASK | \
1091 + RX2_NO_CPU_DSCP_INT_MASK | RX3_NO_CPU_DSCP_INT_MASK | \
1092 + RX4_NO_CPU_DSCP_INT_MASK | RX7_NO_CPU_DSCP_INT_MASK | \
1093 + RX8_NO_CPU_DSCP_INT_MASK | RX9_NO_CPU_DSCP_INT_MASK | \
1094 + RX15_NO_CPU_DSCP_INT_MASK)
1095 +
1096 +/* QDMA_CSR_INT_ENABLE5 */
1097 +#define TX31_COHERENT_INT_MASK BIT(31)
1098 +#define TX30_COHERENT_INT_MASK BIT(30)
1099 +#define TX29_COHERENT_INT_MASK BIT(29)
1100 +#define TX28_COHERENT_INT_MASK BIT(28)
1101 +#define TX27_COHERENT_INT_MASK BIT(27)
1102 +#define TX26_COHERENT_INT_MASK BIT(26)
1103 +#define TX25_COHERENT_INT_MASK BIT(25)
1104 +#define TX24_COHERENT_INT_MASK BIT(24)
1105 +#define TX23_COHERENT_INT_MASK BIT(23)
1106 +#define TX22_COHERENT_INT_MASK BIT(22)
1107 +#define TX21_COHERENT_INT_MASK BIT(21)
1108 +#define TX20_COHERENT_INT_MASK BIT(20)
1109 +#define TX19_COHERENT_INT_MASK BIT(19)
1110 +#define TX18_COHERENT_INT_MASK BIT(18)
1111 +#define TX17_COHERENT_INT_MASK BIT(17)
1112 +#define TX16_COHERENT_INT_MASK BIT(16)
1113 +#define TX15_COHERENT_INT_MASK BIT(15)
1114 +#define TX14_COHERENT_INT_MASK BIT(14)
1115 +#define TX13_COHERENT_INT_MASK BIT(13)
1116 +#define TX12_COHERENT_INT_MASK BIT(12)
1117 +#define TX11_COHERENT_INT_MASK BIT(11)
1118 +#define TX10_COHERENT_INT_MASK BIT(10)
1119 +#define TX9_COHERENT_INT_MASK BIT(9)
1120 +#define TX8_COHERENT_INT_MASK BIT(8)
1121 +
1122 +#define INT_IDX4_MASK \
1123 + (TX8_COHERENT_INT_MASK | TX9_COHERENT_INT_MASK | \
1124 + TX10_COHERENT_INT_MASK | TX11_COHERENT_INT_MASK | \
1125 + TX12_COHERENT_INT_MASK | TX13_COHERENT_INT_MASK | \
1126 + TX14_COHERENT_INT_MASK | TX15_COHERENT_INT_MASK | \
1127 + TX16_COHERENT_INT_MASK | TX17_COHERENT_INT_MASK | \
1128 + TX18_COHERENT_INT_MASK | TX19_COHERENT_INT_MASK | \
1129 + TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK | \
1130 + TX22_COHERENT_INT_MASK | TX23_COHERENT_INT_MASK | \
1131 + TX24_COHERENT_INT_MASK | TX25_COHERENT_INT_MASK | \
1132 + TX26_COHERENT_INT_MASK | TX27_COHERENT_INT_MASK | \
1133 + TX28_COHERENT_INT_MASK | TX29_COHERENT_INT_MASK | \
1134 + TX30_COHERENT_INT_MASK | TX31_COHERENT_INT_MASK)
1135 +
1136 +#define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050)
1137 +
1138 +#define REG_TX_IRQ_CFG(_n) ((_n) ? 0x004c : 0x0054)
1139 +#define TX_IRQ_THR_MASK GENMASK(27, 16)
1140 +#define TX_IRQ_DEPTH_MASK GENMASK(11, 0)
1141 +
1142 +#define REG_IRQ_CLEAR_LEN(_n) ((_n) ? 0x0064 : 0x0058)
1143 +#define IRQ_CLEAR_LEN_MASK GENMASK(7, 0)
1144 +
1145 +#define REG_IRQ_STATUS(_n) ((_n) ? 0x0068 : 0x005c)
1146 +#define IRQ_ENTRY_LEN_MASK GENMASK(27, 16)
1147 +#define IRQ_HEAD_IDX_MASK GENMASK(11, 0)
1148 +
1149 +#define REG_TX_RING_BASE(_n) \
1150 + (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5))
1151 +
1152 +#define REG_TX_RING_BLOCKING(_n) \
1153 + (((_n) < 8) ? 0x0104 + ((_n) << 5) : 0x0b04 + (((_n) - 8) << 5))
1154 +
1155 +#define TX_RING_IRQ_BLOCKING_MAP_MASK BIT(6)
1156 +#define TX_RING_IRQ_BLOCKING_CFG_MASK BIT(4)
1157 +#define TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK BIT(2)
1158 +#define TX_RING_IRQ_BLOCKING_MAX_TH_TXRING_EN_MASK BIT(1)
1159 +#define TX_RING_IRQ_BLOCKING_MIN_TH_TXRING_EN_MASK BIT(0)
1160 +
1161 +#define REG_TX_CPU_IDX(_n) \
1162 + (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5))
1163 +
1164 +#define TX_RING_CPU_IDX_MASK GENMASK(15, 0)
1165 +
1166 +#define REG_TX_DMA_IDX(_n) \
1167 + (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5))
1168 +
1169 +#define TX_RING_DMA_IDX_MASK GENMASK(15, 0)
1170 +
1171 +#define IRQ_RING_IDX_MASK GENMASK(20, 16)
1172 +#define IRQ_DESC_IDX_MASK GENMASK(15, 0)
1173 +
1174 +#define REG_RX_RING_BASE(_n) \
1175 + (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5))
1176 +
1177 +#define REG_RX_RING_SIZE(_n) \
1178 + (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5))
1179 +
1180 +#define RX_RING_THR_MASK GENMASK(31, 16)
1181 +#define RX_RING_SIZE_MASK GENMASK(15, 0)
1182 +
1183 +#define REG_RX_CPU_IDX(_n) \
1184 + (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5))
1185 +
1186 +#define RX_RING_CPU_IDX_MASK GENMASK(15, 0)
1187 +
1188 +#define REG_RX_DMA_IDX(_n) \
1189 + (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5))
1190 +
1191 +#define REG_RX_DELAY_INT_IDX(_n) \
1192 + (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
1193 +
1194 +#define RX_DELAY_INT_MASK GENMASK(15, 0)
1195 +
1196 +#define RX_RING_DMA_IDX_MASK GENMASK(15, 0)
1197 +
1198 +#define REG_INGRESS_TRTCM_CFG 0x0070
1199 +#define INGRESS_TRTCM_EN_MASK BIT(31)
1200 +#define INGRESS_TRTCM_MODE_MASK BIT(30)
1201 +#define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
1202 +#define INGRESS_FAST_TICK_MASK GENMASK(15, 0)
1203 +
1204 +#define REG_QUEUE_CLOSE_CFG(_n) (0x00a0 + ((_n) & 0xfc))
1205 +#define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) BIT((_m) + (((_n) & 0x3) << 3))
1206 +
1207 +#define REG_TXQ_DIS_CFG_BASE(_n) ((_n) ? 0x20a0 : 0x00a0)
1208 +#define REG_TXQ_DIS_CFG(_n, _m) (REG_TXQ_DIS_CFG_BASE((_n)) + (_m) << 2)
1209 +
1210 +#define REG_CNTR_CFG(_n) (0x0400 + ((_n) << 3))
1211 +#define CNTR_EN_MASK BIT(31)
1212 +#define CNTR_ALL_CHAN_EN_MASK BIT(30)
1213 +#define CNTR_ALL_QUEUE_EN_MASK BIT(29)
1214 +#define CNTR_ALL_DSCP_RING_EN_MASK BIT(28)
1215 +#define CNTR_SRC_MASK GENMASK(27, 24)
1216 +#define CNTR_DSCP_RING_MASK GENMASK(20, 16)
1217 +#define CNTR_CHAN_MASK GENMASK(7, 3)
1218 +#define CNTR_QUEUE_MASK GENMASK(2, 0)
1219 +
1220 +#define REG_CNTR_VAL(_n) (0x0404 + ((_n) << 3))
1221 +
1222 +#define REG_LMGR_INIT_CFG 0x1000
1223 +#define LMGR_INIT_START BIT(31)
1224 +#define LMGR_SRAM_MODE_MASK BIT(30)
1225 +#define HW_FWD_PKTSIZE_OVERHEAD_MASK GENMASK(27, 20)
1226 +#define HW_FWD_DESC_NUM_MASK GENMASK(16, 0)
1227 +
1228 +#define REG_FWD_DSCP_LOW_THR 0x1004
1229 +#define FWD_DSCP_LOW_THR_MASK GENMASK(17, 0)
1230 +
1231 +#define REG_EGRESS_RATE_METER_CFG 0x100c
1232 +#define EGRESS_RATE_METER_EN_MASK BIT(31)
1233 +#define EGRESS_RATE_METER_EQ_RATE_EN_MASK BIT(17)
1234 +#define EGRESS_RATE_METER_WINDOW_SZ_MASK GENMASK(16, 12)
1235 +#define EGRESS_RATE_METER_TIMESLICE_MASK GENMASK(10, 0)
1236 +
1237 +#define REG_EGRESS_TRTCM_CFG 0x1010
1238 +#define EGRESS_TRTCM_EN_MASK BIT(31)
1239 +#define EGRESS_TRTCM_MODE_MASK BIT(30)
1240 +#define EGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
1241 +#define EGRESS_FAST_TICK_MASK GENMASK(15, 0)
1242 +
1243 +#define TRTCM_PARAM_RW_MASK BIT(31)
1244 +#define TRTCM_PARAM_RW_DONE_MASK BIT(30)
1245 +#define TRTCM_PARAM_TYPE_MASK GENMASK(29, 28)
1246 +#define TRTCM_METER_GROUP_MASK GENMASK(27, 26)
1247 +#define TRTCM_PARAM_INDEX_MASK GENMASK(23, 17)
1248 +#define TRTCM_PARAM_RATE_TYPE_MASK BIT(16)
1249 +
1250 +#define REG_TRTCM_CFG_PARAM(_n) ((_n) + 0x4)
1251 +#define REG_TRTCM_DATA_LOW(_n) ((_n) + 0x8)
1252 +#define REG_TRTCM_DATA_HIGH(_n) ((_n) + 0xc)
1253 +
1254 +#define REG_TXWRR_MODE_CFG 0x1020
1255 +#define TWRR_WEIGHT_SCALE_MASK BIT(31)
1256 +#define TWRR_WEIGHT_BASE_MASK BIT(3)
1257 +
1258 +#define REG_TXWRR_WEIGHT_CFG 0x1024
1259 +#define TWRR_RW_CMD_MASK BIT(31)
1260 +#define TWRR_RW_CMD_DONE BIT(30)
1261 +#define TWRR_CHAN_IDX_MASK GENMASK(23, 19)
1262 +#define TWRR_QUEUE_IDX_MASK GENMASK(18, 16)
1263 +#define TWRR_VALUE_MASK GENMASK(15, 0)
1264 +
1265 +#define REG_PSE_BUF_USAGE_CFG 0x1028
1266 +#define PSE_BUF_ESTIMATE_EN_MASK BIT(29)
1267 +
1268 +#define REG_CHAN_QOS_MODE(_n) (0x1040 + ((_n) << 2))
1269 +#define CHAN_QOS_MODE_MASK(_n) GENMASK(2 + ((_n) << 2), (_n) << 2)
1270 +
1271 +#define REG_GLB_TRTCM_CFG 0x1080
1272 +#define GLB_TRTCM_EN_MASK BIT(31)
1273 +#define GLB_TRTCM_MODE_MASK BIT(30)
1274 +#define GLB_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
1275 +#define GLB_FAST_TICK_MASK GENMASK(15, 0)
1276 +
1277 +#define REG_TXQ_CNGST_CFG 0x10a0
1278 +#define TXQ_CNGST_DROP_EN BIT(31)
1279 +#define TXQ_CNGST_DEI_DROP_EN BIT(30)
1280 +
1281 +#define REG_SLA_TRTCM_CFG 0x1150
1282 +#define SLA_TRTCM_EN_MASK BIT(31)
1283 +#define SLA_TRTCM_MODE_MASK BIT(30)
1284 +#define SLA_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
1285 +#define SLA_FAST_TICK_MASK GENMASK(15, 0)
1286 +
1287 +/* CTRL */
1288 +#define QDMA_DESC_DONE_MASK BIT(31)
1289 +#define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */
1290 +#define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */
1291 +#define QDMA_DESC_DEI_MASK BIT(25)
1292 +#define QDMA_DESC_NO_DROP_MASK BIT(24)
1293 +#define QDMA_DESC_LEN_MASK GENMASK(15, 0)
1294 +/* DATA */
1295 +#define QDMA_DESC_NEXT_ID_MASK GENMASK(15, 0)
1296 +/* TX MSG0 */
1297 +#define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30)
1298 +#define QDMA_ETH_TXMSG_SP_TAG_MASK GENMASK(29, 14)
1299 +#define QDMA_ETH_TXMSG_ICO_MASK BIT(13)
1300 +#define QDMA_ETH_TXMSG_UCO_MASK BIT(12)
1301 +#define QDMA_ETH_TXMSG_TCO_MASK BIT(11)
1302 +#define QDMA_ETH_TXMSG_TSO_MASK BIT(10)
1303 +#define QDMA_ETH_TXMSG_FAST_MASK BIT(9)
1304 +#define QDMA_ETH_TXMSG_OAM_MASK BIT(8)
1305 +#define QDMA_ETH_TXMSG_CHAN_MASK GENMASK(7, 3)
1306 +#define QDMA_ETH_TXMSG_QUEUE_MASK GENMASK(2, 0)
1307 +/* TX MSG1 */
1308 +#define QDMA_ETH_TXMSG_NO_DROP BIT(31)
1309 +#define QDMA_ETH_TXMSG_METER_MASK GENMASK(30, 24) /* 0x7f no meters */
1310 +#define QDMA_ETH_TXMSG_FPORT_MASK GENMASK(23, 20)
1311 +#define QDMA_ETH_TXMSG_NBOQ_MASK GENMASK(19, 15)
1312 +#define QDMA_ETH_TXMSG_HWF_MASK BIT(14)
1313 +#define QDMA_ETH_TXMSG_HOP_MASK BIT(13)
1314 +#define QDMA_ETH_TXMSG_PTP_MASK BIT(12)
1315 +#define QDMA_ETH_TXMSG_ACNT_G1_MASK GENMASK(10, 6) /* 0x1f do not count */
1316 +#define QDMA_ETH_TXMSG_ACNT_G0_MASK GENMASK(5, 0) /* 0x3f do not count */
1317 +
1318 +/* RX MSG1 */
1319 +#define QDMA_ETH_RXMSG_DEI_MASK BIT(31)
1320 +#define QDMA_ETH_RXMSG_IP6_MASK BIT(30)
1321 +#define QDMA_ETH_RXMSG_IP4_MASK BIT(29)
1322 +#define QDMA_ETH_RXMSG_IP4F_MASK BIT(28)
1323 +#define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27)
1324 +#define QDMA_ETH_RXMSG_L4F_MASK BIT(26)
1325 +#define QDMA_ETH_RXMSG_SPORT_MASK GENMASK(25, 21)
1326 +#define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16)
1327 +#define QDMA_ETH_RXMSG_PPE_ENTRY_MASK GENMASK(15, 0)
1328 +
1329 +struct airoha_qdma_desc {
1330 + __le32 rsv;
1331 + __le32 ctrl;
1332 + __le32 addr;
1333 + __le32 data;
1334 + __le32 msg0;
1335 + __le32 msg1;
1336 + __le32 msg2;
1337 + __le32 msg3;
1338 +};
1339 +
1340 +/* CTRL0 */
1341 +#define QDMA_FWD_DESC_CTX_MASK BIT(31)
1342 +#define QDMA_FWD_DESC_RING_MASK GENMASK(30, 28)
1343 +#define QDMA_FWD_DESC_IDX_MASK GENMASK(27, 16)
1344 +#define QDMA_FWD_DESC_LEN_MASK GENMASK(15, 0)
1345 +/* CTRL1 */
1346 +#define QDMA_FWD_DESC_FIRST_IDX_MASK GENMASK(15, 0)
1347 +/* CTRL2 */
1348 +#define QDMA_FWD_DESC_MORE_PKT_NUM_MASK GENMASK(2, 0)
1349 +
1350 +struct airoha_qdma_fwd_desc {
1351 + __le32 addr;
1352 + __le32 ctrl0;
1353 + __le32 ctrl1;
1354 + __le32 ctrl2;
1355 + __le32 msg0;
1356 + __le32 msg1;
1357 + __le32 rsv0;
1358 + __le32 rsv1;
1359 +};
1360 +
1361 +#endif /* AIROHA_REGS_H */
Ted Hess staging tree