git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 6e45549f4dac42748d66462e04f940ef6737289d Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Tue, 17 Dec 2024 16:39:16 +0800
   4 Subject: [PATCH 01/10] clk: mediatek: mt7629: fix parent clock of some top
   5  clock muxes
   6
   7 According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
   8 shares the same parent selection with CLK_TOP_IRRX_SEL, while the
   9 present parent selection for CLK_TOP_F10M_REF_SEL is actually used
  10 for CLK_TOP_SGMII_REF_1_SEL.
  11
  12 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  13 ---
  14  drivers/clk/mediatek/clk-mt7629.c | 6 +++---
  15  1 file changed, 3 insertions(+), 3 deletions(-)
  16
  17 --- a/drivers/clk/mediatek/clk-mt7629.c
  18 +++ b/drivers/clk/mediatek/clk-mt7629.c
  19 @@ -186,7 +186,7 @@ static const int pwm_parents[] = {
  20         CLK_TOP_UNIVPLL2_D4
  21  };
  22
  23 -static const int f10m_ref_parents[] = {
  24 +static const int sgmii_ref_1_parents[] = {
  25         CLK_XTAL,
  26         CLK_TOP_SGMIIPLL_D2
  27  };
  28 @@ -369,7 +369,7 @@ static const struct mtk_composite top_mu
  29
  30         /* CLK_CFG_1 */
  31         MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
  32 -       MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
  33 +       MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15),
  34         MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
  35         MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
  36
  37 @@ -412,7 +412,7 @@ static const struct mtk_composite top_mu
  38
  39         /* CLK_CFG_8 */
  40         MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
  41 -       MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
  42 +       MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15),
  43         MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
  44  };
  45