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1 From 457d9772e8a5cdae64f66b5f7d5b0247365191ec Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Tue, 1 Apr 2025 15:50:21 +0200
4 Subject: [PATCH] pinctrl: airoha: fix wrong PHY LED mapping and PHY2 LED
5 defines
6
7 The current PHY2 LED define are wrong and actually set BITs outside the
8 related mask. Fix it and set the correct value. While at it, also use
9 FIELD_PREP_CONST macro to make it simple to understand what values are
10 actually applied for the mask.
11
12 Also fix wrong PHY LED mapping. The SoC Switch supports up to 4 port but
13 the register define mapping for 5 PHY port, starting from 0. The mapping
14 was wrongly defined starting from PHY1. Reorder the function group to
15 start from PHY0. PHY4 is actually never supported as we don't have a
16 GPIO pin to assign.
17
18 Cc: stable@vger.kernel.org
19 Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
20 Reviewed-by: Benjamin Larsson <benjamin.larsson@genexis.eu>
21 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
22 Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
23 Link: https://lore.kernel.org/20250401135026.18018-1-ansuelsmth@gmail.com
24 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
25 ---
26 drivers/pinctrl/mediatek/pinctrl-airoha.c | 159 ++++++++++------------
27 1 file changed, 70 insertions(+), 89 deletions(-)
28
29 --- a/drivers/pinctrl/mediatek/pinctrl-airoha.c
30 +++ b/drivers/pinctrl/mediatek/pinctrl-airoha.c
31 @@ -6,6 +6,7 @@
32 */
33
34 #include <dt-bindings/pinctrl/mt65xx.h>
35 +#include <linux/bitfield.h>
36 #include <linux/bits.h>
37 #include <linux/cleanup.h>
38 #include <linux/gpio/driver.h>
39 @@ -106,39 +107,19 @@
40 #define REG_LAN_LED1_MAPPING 0x0280
41
42 #define LAN4_LED_MAPPING_MASK GENMASK(18, 16)
43 -#define LAN4_PHY4_LED_MAP BIT(18)
44 -#define LAN4_PHY2_LED_MAP BIT(17)
45 -#define LAN4_PHY1_LED_MAP BIT(16)
46 -#define LAN4_PHY0_LED_MAP 0
47 -#define LAN4_PHY3_LED_MAP GENMASK(17, 16)
48 +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
49
50 #define LAN3_LED_MAPPING_MASK GENMASK(14, 12)
51 -#define LAN3_PHY4_LED_MAP BIT(14)
52 -#define LAN3_PHY2_LED_MAP BIT(13)
53 -#define LAN3_PHY1_LED_MAP BIT(12)
54 -#define LAN3_PHY0_LED_MAP 0
55 -#define LAN3_PHY3_LED_MAP GENMASK(13, 12)
56 +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
57
58 #define LAN2_LED_MAPPING_MASK GENMASK(10, 8)
59 -#define LAN2_PHY4_LED_MAP BIT(12)
60 -#define LAN2_PHY2_LED_MAP BIT(11)
61 -#define LAN2_PHY1_LED_MAP BIT(10)
62 -#define LAN2_PHY0_LED_MAP 0
63 -#define LAN2_PHY3_LED_MAP GENMASK(11, 10)
64 +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
65
66 #define LAN1_LED_MAPPING_MASK GENMASK(6, 4)
67 -#define LAN1_PHY4_LED_MAP BIT(6)
68 -#define LAN1_PHY2_LED_MAP BIT(5)
69 -#define LAN1_PHY1_LED_MAP BIT(4)
70 -#define LAN1_PHY0_LED_MAP 0
71 -#define LAN1_PHY3_LED_MAP GENMASK(5, 4)
72 +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
73
74 #define LAN0_LED_MAPPING_MASK GENMASK(2, 0)
75 -#define LAN0_PHY4_LED_MAP BIT(3)
76 -#define LAN0_PHY2_LED_MAP BIT(2)
77 -#define LAN0_PHY1_LED_MAP BIT(1)
78 -#define LAN0_PHY0_LED_MAP 0
79 -#define LAN0_PHY3_LED_MAP GENMASK(2, 1)
80 +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
81
82 /* CONF */
83 #define REG_I2C_SDA_E2 0x001c
84 @@ -1470,8 +1451,8 @@ static const struct airoha_pinctrl_func_
85 .regmap[1] = {
86 AIROHA_FUNC_MUX,
87 REG_LAN_LED0_MAPPING,
88 - LAN1_LED_MAPPING_MASK,
89 - LAN1_PHY1_LED_MAP
90 + LAN0_LED_MAPPING_MASK,
91 + LAN0_PHY_LED_MAP(0)
92 },
93 .regmap_size = 2,
94 }, {
95 @@ -1485,8 +1466,8 @@ static const struct airoha_pinctrl_func_
96 .regmap[1] = {
97 AIROHA_FUNC_MUX,
98 REG_LAN_LED0_MAPPING,
99 - LAN2_LED_MAPPING_MASK,
100 - LAN2_PHY1_LED_MAP
101 + LAN1_LED_MAPPING_MASK,
102 + LAN1_PHY_LED_MAP(0)
103 },
104 .regmap_size = 2,
105 }, {
106 @@ -1500,8 +1481,8 @@ static const struct airoha_pinctrl_func_
107 .regmap[1] = {
108 AIROHA_FUNC_MUX,
109 REG_LAN_LED0_MAPPING,
110 - LAN3_LED_MAPPING_MASK,
111 - LAN3_PHY1_LED_MAP
112 + LAN2_LED_MAPPING_MASK,
113 + LAN2_PHY_LED_MAP(0)
114 },
115 .regmap_size = 2,
116 }, {
117 @@ -1515,8 +1496,8 @@ static const struct airoha_pinctrl_func_
118 .regmap[1] = {
119 AIROHA_FUNC_MUX,
120 REG_LAN_LED0_MAPPING,
121 - LAN4_LED_MAPPING_MASK,
122 - LAN4_PHY1_LED_MAP
123 + LAN3_LED_MAPPING_MASK,
124 + LAN3_PHY_LED_MAP(0)
125 },
126 .regmap_size = 2,
127 },
128 @@ -1534,8 +1515,8 @@ static const struct airoha_pinctrl_func_
129 .regmap[1] = {
130 AIROHA_FUNC_MUX,
131 REG_LAN_LED0_MAPPING,
132 - LAN1_LED_MAPPING_MASK,
133 - LAN1_PHY2_LED_MAP
134 + LAN0_LED_MAPPING_MASK,
135 + LAN0_PHY_LED_MAP(1)
136 },
137 .regmap_size = 2,
138 }, {
139 @@ -1549,8 +1530,8 @@ static const struct airoha_pinctrl_func_
140 .regmap[1] = {
141 AIROHA_FUNC_MUX,
142 REG_LAN_LED0_MAPPING,
143 - LAN2_LED_MAPPING_MASK,
144 - LAN2_PHY2_LED_MAP
145 + LAN1_LED_MAPPING_MASK,
146 + LAN1_PHY_LED_MAP(1)
147 },
148 .regmap_size = 2,
149 }, {
150 @@ -1564,8 +1545,8 @@ static const struct airoha_pinctrl_func_
151 .regmap[1] = {
152 AIROHA_FUNC_MUX,
153 REG_LAN_LED0_MAPPING,
154 - LAN3_LED_MAPPING_MASK,
155 - LAN3_PHY2_LED_MAP
156 + LAN2_LED_MAPPING_MASK,
157 + LAN2_PHY_LED_MAP(1)
158 },
159 .regmap_size = 2,
160 }, {
161 @@ -1579,8 +1560,8 @@ static const struct airoha_pinctrl_func_
162 .regmap[1] = {
163 AIROHA_FUNC_MUX,
164 REG_LAN_LED0_MAPPING,
165 - LAN4_LED_MAPPING_MASK,
166 - LAN4_PHY2_LED_MAP
167 + LAN3_LED_MAPPING_MASK,
168 + LAN3_PHY_LED_MAP(1)
169 },
170 .regmap_size = 2,
171 },
172 @@ -1598,8 +1579,8 @@ static const struct airoha_pinctrl_func_
173 .regmap[1] = {
174 AIROHA_FUNC_MUX,
175 REG_LAN_LED0_MAPPING,
176 - LAN1_LED_MAPPING_MASK,
177 - LAN1_PHY3_LED_MAP
178 + LAN0_LED_MAPPING_MASK,
179 + LAN0_PHY_LED_MAP(2)
180 },
181 .regmap_size = 2,
182 }, {
183 @@ -1613,8 +1594,8 @@ static const struct airoha_pinctrl_func_
184 .regmap[1] = {
185 AIROHA_FUNC_MUX,
186 REG_LAN_LED0_MAPPING,
187 - LAN2_LED_MAPPING_MASK,
188 - LAN2_PHY3_LED_MAP
189 + LAN1_LED_MAPPING_MASK,
190 + LAN1_PHY_LED_MAP(2)
191 },
192 .regmap_size = 2,
193 }, {
194 @@ -1628,8 +1609,8 @@ static const struct airoha_pinctrl_func_
195 .regmap[1] = {
196 AIROHA_FUNC_MUX,
197 REG_LAN_LED0_MAPPING,
198 - LAN3_LED_MAPPING_MASK,
199 - LAN3_PHY3_LED_MAP
200 + LAN2_LED_MAPPING_MASK,
201 + LAN2_PHY_LED_MAP(2)
202 },
203 .regmap_size = 2,
204 }, {
205 @@ -1643,8 +1624,8 @@ static const struct airoha_pinctrl_func_
206 .regmap[1] = {
207 AIROHA_FUNC_MUX,
208 REG_LAN_LED0_MAPPING,
209 - LAN4_LED_MAPPING_MASK,
210 - LAN4_PHY3_LED_MAP
211 + LAN3_LED_MAPPING_MASK,
212 + LAN3_PHY_LED_MAP(2)
213 },
214 .regmap_size = 2,
215 },
216 @@ -1662,8 +1643,8 @@ static const struct airoha_pinctrl_func_
217 .regmap[1] = {
218 AIROHA_FUNC_MUX,
219 REG_LAN_LED0_MAPPING,
220 - LAN1_LED_MAPPING_MASK,
221 - LAN1_PHY4_LED_MAP
222 + LAN0_LED_MAPPING_MASK,
223 + LAN0_PHY_LED_MAP(3)
224 },
225 .regmap_size = 2,
226 }, {
227 @@ -1677,8 +1658,8 @@ static const struct airoha_pinctrl_func_
228 .regmap[1] = {
229 AIROHA_FUNC_MUX,
230 REG_LAN_LED0_MAPPING,
231 - LAN2_LED_MAPPING_MASK,
232 - LAN2_PHY4_LED_MAP
233 + LAN1_LED_MAPPING_MASK,
234 + LAN1_PHY_LED_MAP(3)
235 },
236 .regmap_size = 2,
237 }, {
238 @@ -1692,8 +1673,8 @@ static const struct airoha_pinctrl_func_
239 .regmap[1] = {
240 AIROHA_FUNC_MUX,
241 REG_LAN_LED0_MAPPING,
242 - LAN3_LED_MAPPING_MASK,
243 - LAN3_PHY4_LED_MAP
244 + LAN2_LED_MAPPING_MASK,
245 + LAN2_PHY_LED_MAP(3)
246 },
247 .regmap_size = 2,
248 }, {
249 @@ -1707,8 +1688,8 @@ static const struct airoha_pinctrl_func_
250 .regmap[1] = {
251 AIROHA_FUNC_MUX,
252 REG_LAN_LED0_MAPPING,
253 - LAN4_LED_MAPPING_MASK,
254 - LAN4_PHY4_LED_MAP
255 + LAN3_LED_MAPPING_MASK,
256 + LAN3_PHY_LED_MAP(3)
257 },
258 .regmap_size = 2,
259 },
260 @@ -1726,8 +1707,8 @@ static const struct airoha_pinctrl_func_
261 .regmap[1] = {
262 AIROHA_FUNC_MUX,
263 REG_LAN_LED1_MAPPING,
264 - LAN1_LED_MAPPING_MASK,
265 - LAN1_PHY1_LED_MAP
266 + LAN0_LED_MAPPING_MASK,
267 + LAN0_PHY_LED_MAP(0)
268 },
269 .regmap_size = 2,
270 }, {
271 @@ -1741,8 +1722,8 @@ static const struct airoha_pinctrl_func_
272 .regmap[1] = {
273 AIROHA_FUNC_MUX,
274 REG_LAN_LED1_MAPPING,
275 - LAN2_LED_MAPPING_MASK,
276 - LAN2_PHY1_LED_MAP
277 + LAN1_LED_MAPPING_MASK,
278 + LAN1_PHY_LED_MAP(0)
279 },
280 .regmap_size = 2,
281 }, {
282 @@ -1756,8 +1737,8 @@ static const struct airoha_pinctrl_func_
283 .regmap[1] = {
284 AIROHA_FUNC_MUX,
285 REG_LAN_LED1_MAPPING,
286 - LAN3_LED_MAPPING_MASK,
287 - LAN3_PHY1_LED_MAP
288 + LAN2_LED_MAPPING_MASK,
289 + LAN2_PHY_LED_MAP(0)
290 },
291 .regmap_size = 2,
292 }, {
293 @@ -1771,8 +1752,8 @@ static const struct airoha_pinctrl_func_
294 .regmap[1] = {
295 AIROHA_FUNC_MUX,
296 REG_LAN_LED1_MAPPING,
297 - LAN4_LED_MAPPING_MASK,
298 - LAN4_PHY1_LED_MAP
299 + LAN3_LED_MAPPING_MASK,
300 + LAN3_PHY_LED_MAP(0)
301 },
302 .regmap_size = 2,
303 },
304 @@ -1790,8 +1771,8 @@ static const struct airoha_pinctrl_func_
305 .regmap[1] = {
306 AIROHA_FUNC_MUX,
307 REG_LAN_LED1_MAPPING,
308 - LAN1_LED_MAPPING_MASK,
309 - LAN1_PHY2_LED_MAP
310 + LAN0_LED_MAPPING_MASK,
311 + LAN0_PHY_LED_MAP(1)
312 },
313 .regmap_size = 2,
314 }, {
315 @@ -1805,8 +1786,8 @@ static const struct airoha_pinctrl_func_
316 .regmap[1] = {
317 AIROHA_FUNC_MUX,
318 REG_LAN_LED1_MAPPING,
319 - LAN2_LED_MAPPING_MASK,
320 - LAN2_PHY2_LED_MAP
321 + LAN1_LED_MAPPING_MASK,
322 + LAN1_PHY_LED_MAP(1)
323 },
324 .regmap_size = 2,
325 }, {
326 @@ -1820,8 +1801,8 @@ static const struct airoha_pinctrl_func_
327 .regmap[1] = {
328 AIROHA_FUNC_MUX,
329 REG_LAN_LED1_MAPPING,
330 - LAN3_LED_MAPPING_MASK,
331 - LAN3_PHY2_LED_MAP
332 + LAN2_LED_MAPPING_MASK,
333 + LAN2_PHY_LED_MAP(1)
334 },
335 .regmap_size = 2,
336 }, {
337 @@ -1835,8 +1816,8 @@ static const struct airoha_pinctrl_func_
338 .regmap[1] = {
339 AIROHA_FUNC_MUX,
340 REG_LAN_LED1_MAPPING,
341 - LAN4_LED_MAPPING_MASK,
342 - LAN4_PHY2_LED_MAP
343 + LAN3_LED_MAPPING_MASK,
344 + LAN3_PHY_LED_MAP(1)
345 },
346 .regmap_size = 2,
347 },
348 @@ -1854,8 +1835,8 @@ static const struct airoha_pinctrl_func_
349 .regmap[1] = {
350 AIROHA_FUNC_MUX,
351 REG_LAN_LED1_MAPPING,
352 - LAN1_LED_MAPPING_MASK,
353 - LAN1_PHY3_LED_MAP
354 + LAN0_LED_MAPPING_MASK,
355 + LAN0_PHY_LED_MAP(2)
356 },
357 .regmap_size = 2,
358 }, {
359 @@ -1869,8 +1850,8 @@ static const struct airoha_pinctrl_func_
360 .regmap[1] = {
361 AIROHA_FUNC_MUX,
362 REG_LAN_LED1_MAPPING,
363 - LAN2_LED_MAPPING_MASK,
364 - LAN2_PHY3_LED_MAP
365 + LAN1_LED_MAPPING_MASK,
366 + LAN1_PHY_LED_MAP(2)
367 },
368 .regmap_size = 2,
369 }, {
370 @@ -1884,8 +1865,8 @@ static const struct airoha_pinctrl_func_
371 .regmap[1] = {
372 AIROHA_FUNC_MUX,
373 REG_LAN_LED1_MAPPING,
374 - LAN3_LED_MAPPING_MASK,
375 - LAN3_PHY3_LED_MAP
376 + LAN2_LED_MAPPING_MASK,
377 + LAN2_PHY_LED_MAP(2)
378 },
379 .regmap_size = 2,
380 }, {
381 @@ -1899,8 +1880,8 @@ static const struct airoha_pinctrl_func_
382 .regmap[1] = {
383 AIROHA_FUNC_MUX,
384 REG_LAN_LED1_MAPPING,
385 - LAN4_LED_MAPPING_MASK,
386 - LAN4_PHY3_LED_MAP
387 + LAN3_LED_MAPPING_MASK,
388 + LAN3_PHY_LED_MAP(2)
389 },
390 .regmap_size = 2,
391 },
392 @@ -1918,8 +1899,8 @@ static const struct airoha_pinctrl_func_
393 .regmap[1] = {
394 AIROHA_FUNC_MUX,
395 REG_LAN_LED1_MAPPING,
396 - LAN1_LED_MAPPING_MASK,
397 - LAN1_PHY4_LED_MAP
398 + LAN0_LED_MAPPING_MASK,
399 + LAN0_PHY_LED_MAP(3)
400 },
401 .regmap_size = 2,
402 }, {
403 @@ -1933,8 +1914,8 @@ static const struct airoha_pinctrl_func_
404 .regmap[1] = {
405 AIROHA_FUNC_MUX,
406 REG_LAN_LED1_MAPPING,
407 - LAN2_LED_MAPPING_MASK,
408 - LAN2_PHY4_LED_MAP
409 + LAN1_LED_MAPPING_MASK,
410 + LAN1_PHY_LED_MAP(3)
411 },
412 .regmap_size = 2,
413 }, {
414 @@ -1948,8 +1929,8 @@ static const struct airoha_pinctrl_func_
415 .regmap[1] = {
416 AIROHA_FUNC_MUX,
417 REG_LAN_LED1_MAPPING,
418 - LAN3_LED_MAPPING_MASK,
419 - LAN3_PHY4_LED_MAP
420 + LAN2_LED_MAPPING_MASK,
421 + LAN2_PHY_LED_MAP(3)
422 },
423 .regmap_size = 2,
424 }, {
425 @@ -1963,8 +1944,8 @@ static const struct airoha_pinctrl_func_
426 .regmap[1] = {
427 AIROHA_FUNC_MUX,
428 REG_LAN_LED1_MAPPING,
429 - LAN4_LED_MAPPING_MASK,
430 - LAN4_PHY4_LED_MAP
431 + LAN3_LED_MAPPING_MASK,
432 + LAN3_PHY_LED_MAP(3)
433 },
434 .regmap_size = 2,
435 },
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