git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001
   2 From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
   3 Date: Sun, 23 Feb 2025 11:31:39 +0200
   4 Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
   5
   6 Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
   7 provider support"), the HDMI PHY PLL can be used as an alternative and
   8 more accurate pixel clock source for VOP2 to improve display modes
   9 handling on RK3588 SoC.
  10
  11 Add the missing #clock-cells property to allow using the clock provider
  12 functionality of HDMI1 PHY.
  13
  14 Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
  15 Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com
  16 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  17
  18 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
  19 +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
  20 @@ -446,6 +446,7 @@
  21                 reg = <0x0 0xfed70000 0x0 0x2000>;
  22                 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
  23                 clock-names = "ref", "apb";
  24 +               #clock-cells = <0>;
  25                 #phy-cells = <0>;
  26                 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
  27                          <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,