git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From da447ec387800bdf2df1fb1d8c1522991d025952 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Reichel <sebastian.reichel@collabora.com>
   3 Date: Mon, 18 Sep 2023 16:14:51 +0200
   4 Subject: [PATCH] arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5b
   5
   6 Enable PCIe2_0 controller and its voltage supply, which is routed
   7 to the M.2 E-Key on the upper side of the Radxa Rock 5B.
   8
   9 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
  10 Link: https://lore.kernel.org/r/20230918141451.131247-4-sebastian.reichel@collabora.com
  11 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  12 ---
  13  .../boot/dts/rockchip/rk3588-rock-5b.dts      | 35 +++++++++++++++++++
  14  1 file changed, 35 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
  17 +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
  18 @@ -43,6 +43,21 @@
  19                 #cooling-cells = <2>;
  20         };
  21
  22 +       vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
  23 +               compatible = "regulator-fixed";
  24 +               enable-active-high;
  25 +               gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
  26 +               pinctrl-names = "default";
  27 +               pinctrl-0 = <&pcie2_0_vcc3v3_en>;
  28 +               regulator-name = "vcc3v3_pcie2x1l0";
  29 +               regulator-always-on;
  30 +               regulator-boot-on;
  31 +               regulator-min-microvolt = <3300000>;
  32 +               regulator-max-microvolt = <3300000>;
  33 +               startup-delay-us = <50000>;
  34 +               vin-supply = <&vcc5v0_sys>;
  35 +       };
  36 +
  37         vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "vcc3v3_pcie2x1l2";
  40 @@ -103,6 +118,10 @@
  41         status = "okay";
  42  };
  43
  44 +&combphy1_ps {
  45 +       status = "okay";
  46 +};
  47 +
  48  &cpu_b0 {
  49         cpu-supply = <&vdd_cpu_big0_s0>;
  50  };
  51 @@ -229,6 +248,14 @@
  52         };
  53  };
  54
  55 +&pcie2x1l0 {
  56 +       pinctrl-names = "default";
  57 +       pinctrl-0 = <&pcie2_0_rst>;
  58 +       reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
  59 +       vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
  60 +       status = "okay";
  61 +};
  62 +
  63  &pcie2x1l2 {
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pcie2_2_rst>;
  66 @@ -263,6 +290,14 @@
  67         };
  68
  69         pcie2 {
  70 +               pcie2_0_rst: pcie2-0-rst {
  71 +                       rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
  72 +               };
  73 +
  74 +               pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
  75 +                       rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
  76 +               };
  77 +
  78                 pcie2_2_rst: pcie2-2-rst {
  79                         rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
  80                 };