git.openwrt.org Git - openwrt/staging/linusw.git/blob

   1 From 68320e35f8cb1987b4ad34347fc7033832da99e3 Mon Sep 17 00:00:00 2001
   2 From: Nitheesh Sekar <quic_nsekar@quicinc.com>
   3 Date: Mon, 4 Sep 2023 12:06:33 +0530
   4 Subject: [PATCH] phy: qcom-m31: Add compatible, phy init sequence for IPQ5018
   5
   6 Add phy init sequence and compatible string for IPQ5018
   7 chipset.
   8
   9 Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
  10 Link: https://lore.kernel.org/r/20230904063635.24975-3-quic_nsekar@quicinc.com
  11 Signed-off-by: Vinod Koul <vkoul@kernel.org>
  12 ---
  13  drivers/phy/qualcomm/phy-qcom-m31.c | 51 +++++++++++++++++++++++++++++
  14  1 file changed, 51 insertions(+)
  15
  16 --- a/drivers/phy/qualcomm/phy-qcom-m31.c
  17 +++ b/drivers/phy/qualcomm/phy-qcom-m31.c
  18 @@ -82,6 +82,50 @@ struct m31_priv_data {
  19         unsigned int                    nregs;
  20  };
  21
  22 +static const struct m31_phy_regs m31_ipq5018_regs[] = {
  23 +       {
  24 +               .off = USB_PHY_CFG0,
  25 +               .val = UTMI_PHY_OVERRIDE_EN
  26 +       },
  27 +       {
  28 +               .off = USB_PHY_UTMI_CTRL5,
  29 +               .val = POR_EN,
  30 +               .delay = 15
  31 +       },
  32 +       {
  33 +               .off = USB_PHY_FSEL_SEL,
  34 +               .val = FREQ_SEL
  35 +       },
  36 +       {
  37 +               .off = USB_PHY_HS_PHY_CTRL_COMMON0,
  38 +               .val = COMMONONN | FSEL | RETENABLEN
  39 +       },
  40 +       {
  41 +               .off = USB_PHY_REFCLK_CTRL,
  42 +               .val = CLKCORE
  43 +       },
  44 +       {
  45 +               .off = USB_PHY_UTMI_CTRL5,
  46 +               .val = POR_EN
  47 +       },
  48 +       {
  49 +               .off = USB_PHY_HS_PHY_CTRL2,
  50 +               .val = USB2_SUSPEND_N_SEL | USB2_SUSPEND_N | USB2_UTMI_CLK_EN
  51 +       },
  52 +       {
  53 +               .off = USB_PHY_UTMI_CTRL5,
  54 +               .val = 0x0
  55 +       },
  56 +       {
  57 +               .off = USB_PHY_HS_PHY_CTRL2,
  58 +               .val = USB2_SUSPEND_N | USB2_UTMI_CLK_EN
  59 +       },
  60 +       {
  61 +               .off = USB_PHY_CFG0,
  62 +               .val = 0x0
  63 +       },
  64 +};
  65 +
  66  static struct m31_phy_regs m31_ipq5332_regs[] = {
  67         {
  68                 USB_PHY_CFG0,
  69 @@ -267,6 +311,12 @@ static int m31usb_phy_probe(struct platf
  70         return PTR_ERR_OR_ZERO(phy_provider);
  71  }
  72
  73 +static const struct m31_priv_data m31_ipq5018_data = {
  74 +       .ulpi_mode = false,
  75 +       .regs = m31_ipq5018_regs,
  76 +       .nregs = ARRAY_SIZE(m31_ipq5018_regs),
  77 +};
  78 +
  79  static const struct m31_priv_data m31_ipq5332_data = {
  80         .ulpi_mode = false,
  81         .regs = m31_ipq5332_regs,
  82 @@ -274,6 +324,7 @@ static const struct m31_priv_data m31_ip
  83  };
  84
  85  static const struct of_device_id m31usb_phy_id_table[] = {
  86 +       { .compatible = "qcom,ipq5018-usb-hsphy", .data = &m31_ipq5018_data },
  87         { .compatible = "qcom,ipq5332-usb-hsphy", .data = &m31_ipq5332_data },
  88         { },
  89  };