2136fa224bbb4785afe62ab2d4c06f39a74ba751
[openwrt/staging/stintel.git] /
1 From 47c7ae9715d76054d98e8407dbb8ca1cf42fd587 Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Mon, 9 Dec 2024 17:50:31 +0100
4 Subject: [PATCH] arm64: dts: qcom: add partition table for ipq9574 rdp common
5
6 Add partition table for ipq9574 SoC common to every RDB board.
7
8 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
9 ---
10 .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 146 +++++++++++++++++-
11 1 file changed, 145 insertions(+), 1 deletion(-)
12
13 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
14 +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
15 @@ -74,11 +74,155 @@
16 status = "okay";
17
18 flash@0 {
19 - compatible = "micron,n25q128a11", "jedec,spi-nor";
20 + compatible = "jedec,spi-nor";
21 reg = <0>;
22 #address-cells = <1>;
23 #size-cells = <1>;
24 spi-max-frequency = <50000000>;
25 +
26 + partitions {
27 + compatible = "fixed-partitions";
28 + #address-cells = <1>;
29 + #size-cells = <1>;
30 +
31 + partition@0 {
32 + label = "0:sbl1";
33 + reg = <0x0 0xc0000>;
34 + read-only;
35 + };
36 +
37 + partition@c0000 {
38 + label = "0:mibib";
39 + reg = <0xc0000 0x10000>;
40 + read-only;
41 + };
42 +
43 + partition@d0000 {
44 + label = "0:bootconfig";
45 + reg = <0xd0000 0x20000>;
46 + read-only;
47 + };
48 +
49 + partition@f0000 {
50 + label = "0:bootconfig1";
51 + reg = <0xf0000 0x20000>;
52 + read-only;
53 + };
54 +
55 + partition@110000 {
56 + label = "0:qsee";
57 + reg = <0x110000 0x180000>;
58 + read-only;
59 + };
60 +
61 + partition@290000 {
62 + label = "0:qsee_1";
63 + reg = <0x290000 0x180000>;
64 + read-only;
65 + };
66 +
67 + partition@410000 {
68 + label = "0:devcfg";
69 + reg = <0x410000 0x10000>;
70 + read-only;
71 + };
72 +
73 + partition@420000 {
74 + label = "0:devcfg_1";
75 + reg = <0x420000 0x10000>;
76 + read-only;
77 + };
78 +
79 + partition@430000 {
80 + label = "0:apdp";
81 + reg = <0x430000 0x10000>;
82 + read-only;
83 + };
84 +
85 + partition@440000 {
86 + label = "0:apdp_1";
87 + reg = <0x440000 0x10000>;
88 + read-only;
89 + };
90 +
91 + partition@450000 {
92 + label = "0:tme";
93 + reg = <0x450000 0x40000>;
94 + read-only;
95 + };
96 +
97 + partition@490000 {
98 + label = "0:tme_1";
99 + reg = <0x490000 0x40000>;
100 + read-only;
101 + };
102 +
103 + partition@4d0000 {
104 + label = "0:rpm";
105 + reg = <0x4d0000 0x20000>;
106 + read-only;
107 + };
108 +
109 + partition@4f0000 {
110 + label = "0:rpm_1";
111 + reg = <0x4f0000 0x20000>;
112 + read-only;
113 + };
114 +
115 + partition@510000 {
116 + label = "0:cdt";
117 + reg = <0x510000 0x10000>;
118 + read-only;
119 + };
120 +
121 + partition@520000 {
122 + label = "0:cdt_1";
123 + reg = <0x520000 0x10000>;
124 + read-only;
125 + };
126 +
127 + partition@530000 {
128 + compatible = "u-boot,env";
129 + label = "0:appsblenv";
130 + reg = <0x530000 0x10000>;
131 +
132 + macaddr_lan: ethaddr {
133 + #nvmem-cell-cells = <1>;
134 + };
135 + };
136 +
137 + partition@540000 {
138 + label = "0:appsbl";
139 + reg = <0x540000 0xa0000>;
140 + read-only;
141 + };
142 +
143 + partition@5e0000 {
144 + label = "0:appsbl_1";
145 + reg = <0x5e0000 0xa0000>;
146 + read-only;
147 + };
148 +
149 + partition@680000 {
150 + label = "0:art";
151 + reg = <0x680000 0x100000>;
152 + read-only;
153 + };
154 +
155 + partition@780000 {
156 + label = "0:ethphyfw";
157 + reg = <0x780000 0x80000>;
158 + read-only;
159 +
160 + nvmem-layout {
161 + compatible = "fixed-layout";
162 +
163 + aqr_fw: aqr-fw@0 {
164 + reg = <0x0 0x5fc02>;
165 + };
166 + };
167 + };
168 + };
169 };
170 };
171