1 From 90d4e466c9ea2010f33880a36317a8486ccbe082 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Wed, 8 Jan 2025 10:50:43 +0100
4 Subject: [PATCH 4/6] PCI: mediatek-gen3: Move reset delay in
5 mtk_pcie_en7581_power_up()
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
10 Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal
11 causing occasional PCIe link down issues. In order to overcome the
12 problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and
13 REG_RESET_CONTROL (0x834) registers available in the clock module
14 running clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up().
16 In order to make the code more readable, move the wait for the time
17 needed to complete the PCIe reset from en7581_pci_enable() to
18 mtk_pcie_en7581_power_up().
20 Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value
21 (100ms) since it has no impact on the driver behavior.
23 Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-4-21ac939a3b9b@kernel.org
24 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
25 Signed-off-by: Krzysztof WilczyĆski <kwilczynski@kernel.org>
26 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
27 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
28 Acked-by: Stephen Boyd <sboyd@kernel.org>
30 drivers/clk/clk-en7523.c | 1 -
31 drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++
32 2 files changed, 7 insertions(+), 1 deletion(-)
34 --- a/drivers/clk/clk-en7523.c
35 +++ b/drivers/clk/clk-en7523.c
36 @@ -489,7 +489,6 @@ static int en7581_pci_enable(struct clk_
37 REG_PCI_CONTROL_PERSTOUT;
38 val = readl(np_base + REG_PCI_CONTROL);
39 writel(val | mask, np_base + REG_PCI_CONTROL);
44 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
45 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
46 @@ -936,6 +936,13 @@ static int mtk_pcie_en7581_power_up(stru
47 goto err_clk_prepare_enable;
51 + * Airoha EN7581 performs PCIe reset via clk callbacks since it has a
52 + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to
53 + * complete the PCIe reset.
55 + msleep(PCIE_T_PVPERL_MS);
59 err_clk_prepare_enable: