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1 From 7304d1909080ef0c9da703500a97f46c98393fcd Mon Sep 17 00:00:00 2001
2 From: Md Sadre Alam <quic_mdalam@quicinc.com>
3 Date: Mon, 24 Feb 2025 16:44:14 +0530
4 Subject: [PATCH] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
5
6 This driver implements support for the SPI-NAND mode of QCOM NAND Flash
7 Interface as a SPI-MEM controller with pipelined ECC capability.
8
9 Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
10 Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
11 Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
12 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
13 Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
14 Link: https://patch.msgid.link/20250224111414.2809669-3-quic_mdalam@quicinc.com
15 Signed-off-by: Mark Brown <broonie@kernel.org>
16 ---
17 drivers/mtd/nand/Makefile | 4 +
18 drivers/spi/Kconfig | 9 +
19 drivers/spi/Makefile | 1 +
20 drivers/spi/spi-qpic-snand.c | 1631 ++++++++++++++++++++++++++
21 include/linux/mtd/nand-qpic-common.h | 7 +
22 5 files changed, 1652 insertions(+)
23 create mode 100644 drivers/spi/spi-qpic-snand.c
24
25 --- a/drivers/mtd/nand/Makefile
26 +++ b/drivers/mtd/nand/Makefile
27 @@ -3,7 +3,11 @@
28 nandcore-objs := core.o bbt.o
29 obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
30 obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
31 +ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
32 +obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
33 +else
34 obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
35 +endif
36 obj-y += onenand/
37 obj-y += raw/
38 obj-y += spi/
39 --- a/drivers/spi/Kconfig
40 +++ b/drivers/spi/Kconfig
41 @@ -870,6 +870,15 @@ config SPI_QCOM_QSPI
42 help
43 QSPI(Quad SPI) driver for Qualcomm QSPI controller.
44
45 +config SPI_QPIC_SNAND
46 + bool "QPIC SNAND controller"
47 + depends on ARCH_QCOM || COMPILE_TEST
48 + select MTD
49 + help
50 + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
51 + QPIC controller supports both parallel nand and serial nand.
52 + This config will enable serial nand driver for QPIC controller.
53 +
54 config SPI_QUP
55 tristate "Qualcomm SPI controller with QUP interface"
56 depends on ARCH_QCOM || COMPILE_TEST
57 --- a/drivers/spi/Makefile
58 +++ b/drivers/spi/Makefile
59 @@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-
60 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
61 obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o
62 obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
63 +obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
64 obj-$(CONFIG_SPI_QUP) += spi-qup.o
65 obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
66 obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
67 --- /dev/null
68 +++ b/drivers/spi/spi-qpic-snand.c
69 @@ -0,0 +1,1631 @@
70 +/*
71 + * SPDX-License-Identifier: GPL-2.0
72 + *
73 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
74 + *
75 + * Authors:
76 + * Md Sadre Alam <quic_mdalam@quicinc.com>
77 + * Sricharan R <quic_srichara@quicinc.com>
78 + * Varadarajan Narayanan <quic_varada@quicinc.com>
79 + */
80 +#include <linux/bitops.h>
81 +#include <linux/clk.h>
82 +#include <linux/delay.h>
83 +#include <linux/dmaengine.h>
84 +#include <linux/dma-mapping.h>
85 +#include <linux/dma/qcom_adm.h>
86 +#include <linux/dma/qcom_bam_dma.h>
87 +#include <linux/module.h>
88 +#include <linux/of.h>
89 +#include <linux/platform_device.h>
90 +#include <linux/slab.h>
91 +#include <linux/mtd/nand-qpic-common.h>
92 +#include <linux/mtd/spinand.h>
93 +#include <linux/bitfield.h>
94 +
95 +#define NAND_FLASH_SPI_CFG 0xc0
96 +#define NAND_NUM_ADDR_CYCLES 0xc4
97 +#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
98 +#define NAND_FLASH_FEATURES 0xf64
99 +
100 +/* QSPI NAND config reg bits */
101 +#define LOAD_CLK_CNTR_INIT_EN BIT(28)
102 +#define CLK_CNTR_INIT_VAL_VEC 0x924
103 +#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
104 +#define FEA_STATUS_DEV_ADDR 0xc0
105 +#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
106 +#define SPI_CFG BIT(0)
107 +#define SPI_NUM_ADDR 0xDA4DB
108 +#define SPI_WAIT_CNT 0x10
109 +#define QPIC_QSPI_NUM_CS 1
110 +#define SPI_TRANSFER_MODE_x1 BIT(29)
111 +#define SPI_TRANSFER_MODE_x4 (3 << 29)
112 +#define SPI_WP BIT(28)
113 +#define SPI_HOLD BIT(27)
114 +#define QPIC_SET_FEATURE BIT(31)
115 +
116 +#define SPINAND_RESET 0xff
117 +#define SPINAND_READID 0x9f
118 +#define SPINAND_GET_FEATURE 0x0f
119 +#define SPINAND_SET_FEATURE 0x1f
120 +#define SPINAND_READ 0x13
121 +#define SPINAND_ERASE 0xd8
122 +#define SPINAND_WRITE_EN 0x06
123 +#define SPINAND_PROGRAM_EXECUTE 0x10
124 +#define SPINAND_PROGRAM_LOAD 0x84
125 +
126 +#define ACC_FEATURE 0xe
127 +#define BAD_BLOCK_MARKER_SIZE 0x2
128 +#define OOB_BUF_SIZE 128
129 +#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
130 +
131 +struct qpic_snand_op {
132 + u32 cmd_reg;
133 + u32 addr1_reg;
134 + u32 addr2_reg;
135 +};
136 +
137 +struct snandc_read_status {
138 + __le32 snandc_flash;
139 + __le32 snandc_buffer;
140 + __le32 snandc_erased_cw;
141 +};
142 +
143 +/*
144 + * ECC state struct
145 + * @corrected: ECC corrected
146 + * @bitflips: Max bit flip
147 + * @failed: ECC failed
148 + */
149 +struct qcom_ecc_stats {
150 + u32 corrected;
151 + u32 bitflips;
152 + u32 failed;
153 +};
154 +
155 +struct qpic_ecc {
156 + struct device *dev;
157 + int ecc_bytes_hw;
158 + int spare_bytes;
159 + int bbm_size;
160 + int ecc_mode;
161 + int bytes;
162 + int steps;
163 + int step_size;
164 + int strength;
165 + int cw_size;
166 + int cw_data;
167 + u32 cfg0;
168 + u32 cfg1;
169 + u32 cfg0_raw;
170 + u32 cfg1_raw;
171 + u32 ecc_buf_cfg;
172 + u32 ecc_bch_cfg;
173 + u32 clrflashstatus;
174 + u32 clrreadstatus;
175 + bool bch_enabled;
176 +};
177 +
178 +struct qpic_spi_nand {
179 + struct qcom_nand_controller *snandc;
180 + struct spi_controller *ctlr;
181 + struct mtd_info *mtd;
182 + struct clk *iomacro_clk;
183 + struct qpic_ecc *ecc;
184 + struct qcom_ecc_stats ecc_stats;
185 + struct nand_ecc_engine ecc_eng;
186 + u8 *data_buf;
187 + u8 *oob_buf;
188 + u32 wlen;
189 + __le32 addr1;
190 + __le32 addr2;
191 + __le32 cmd;
192 + u32 num_cw;
193 + bool oob_rw;
194 + bool page_rw;
195 + bool raw_rw;
196 +};
197 +
198 +static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
199 + int reg, int cw_offset, int read_size,
200 + int is_last_read_loc)
201 +{
202 + __le32 locreg_val;
203 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
204 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
205 + << READ_LOCATION_LAST));
206 +
207 + locreg_val = cpu_to_le32(val);
208 +
209 + if (reg == NAND_READ_LOCATION_0)
210 + snandc->regs->read_location0 = locreg_val;
211 + else if (reg == NAND_READ_LOCATION_1)
212 + snandc->regs->read_location1 = locreg_val;
213 + else if (reg == NAND_READ_LOCATION_2)
214 + snandc->regs->read_location1 = locreg_val;
215 + else if (reg == NAND_READ_LOCATION_3)
216 + snandc->regs->read_location3 = locreg_val;
217 +}
218 +
219 +static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
220 + int reg, int cw_offset, int read_size,
221 + int is_last_read_loc)
222 +{
223 + __le32 locreg_val;
224 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
225 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
226 + << READ_LOCATION_LAST));
227 +
228 + locreg_val = cpu_to_le32(val);
229 +
230 + if (reg == NAND_READ_LOCATION_LAST_CW_0)
231 + snandc->regs->read_location_last0 = locreg_val;
232 + else if (reg == NAND_READ_LOCATION_LAST_CW_1)
233 + snandc->regs->read_location_last1 = locreg_val;
234 + else if (reg == NAND_READ_LOCATION_LAST_CW_2)
235 + snandc->regs->read_location_last2 = locreg_val;
236 + else if (reg == NAND_READ_LOCATION_LAST_CW_3)
237 + snandc->regs->read_location_last3 = locreg_val;
238 +}
239 +
240 +static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
241 +{
242 + struct nand_ecc_engine *eng = nand->ecc.engine;
243 + struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
244 +
245 + return qspi->snandc;
246 +}
247 +
248 +static int qcom_spi_init(struct qcom_nand_controller *snandc)
249 +{
250 + u32 snand_cfg_val = 0x0;
251 + int ret;
252 +
253 + snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
254 + FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
255 + FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
256 + FIELD_PREP(SPI_CFG, 0);
257 +
258 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
259 + snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
260 + snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
261 +
262 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
263 +
264 + snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
265 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
266 +
267 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
268 +
269 + qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
270 + qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
271 + NAND_BAM_NEXT_SGL);
272 +
273 + ret = qcom_submit_descs(snandc);
274 + if (ret) {
275 + dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
276 + return ret;
277 + }
278 +
279 + return ret;
280 +}
281 +
282 +static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
283 + struct mtd_oob_region *oobregion)
284 +{
285 + struct nand_device *nand = mtd_to_nanddev(mtd);
286 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
287 + struct qpic_ecc *qecc = snandc->qspi->ecc;
288 +
289 + if (section > 1)
290 + return -ERANGE;
291 +
292 + oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
293 + oobregion->offset = mtd->oobsize - oobregion->length;
294 +
295 + return 0;
296 +}
297 +
298 +static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
299 + struct mtd_oob_region *oobregion)
300 +{
301 + struct nand_device *nand = mtd_to_nanddev(mtd);
302 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
303 + struct qpic_ecc *qecc = snandc->qspi->ecc;
304 +
305 + if (section)
306 + return -ERANGE;
307 +
308 + oobregion->length = qecc->steps * 4;
309 + oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
310 +
311 + return 0;
312 +}
313 +
314 +static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
315 + .ecc = qcom_spi_ooblayout_ecc,
316 + .free = qcom_spi_ooblayout_free,
317 +};
318 +
319 +static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
320 +{
321 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
322 + struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
323 + struct mtd_info *mtd = nanddev_to_mtd(nand);
324 + int cwperpage, bad_block_byte;
325 + struct qpic_ecc *ecc_cfg;
326 +
327 + cwperpage = mtd->writesize / NANDC_STEP_SIZE;
328 + snandc->qspi->num_cw = cwperpage;
329 +
330 + ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
331 + if (!ecc_cfg)
332 + return -ENOMEM;
333 + snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize,
334 + GFP_KERNEL);
335 + if (!snandc->qspi->oob_buf)
336 + return -ENOMEM;
337 +
338 + memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
339 +
340 + nand->ecc.ctx.priv = ecc_cfg;
341 + snandc->qspi->mtd = mtd;
342 +
343 + ecc_cfg->ecc_bytes_hw = 7;
344 + ecc_cfg->spare_bytes = 4;
345 + ecc_cfg->bbm_size = 1;
346 + ecc_cfg->bch_enabled = true;
347 + ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
348 +
349 + ecc_cfg->steps = 4;
350 + ecc_cfg->strength = 4;
351 + ecc_cfg->step_size = 512;
352 + ecc_cfg->cw_data = 516;
353 + ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
354 + bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
355 +
356 + mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
357 +
358 + ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
359 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
360 + FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
361 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
362 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
363 + FIELD_PREP(STATUS_BFR_READ, 0) |
364 + FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
365 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
366 +
367 + ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
368 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
369 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
370 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
371 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
372 + FIELD_PREP(WIDE_FLASH, 0) |
373 + FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
374 +
375 + ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
376 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
377 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
378 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
379 +
380 + ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
381 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
382 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
383 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
384 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
385 + FIELD_PREP(WIDE_FLASH, 0) |
386 + FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
387 +
388 + ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
389 + FIELD_PREP(ECC_SW_RESET, 0) |
390 + FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
391 + FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
392 + FIELD_PREP(ECC_MODE_MASK, 0) |
393 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
394 +
395 + ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
396 + ecc_cfg->clrflashstatus = FS_READY_BSY_N;
397 + ecc_cfg->clrreadstatus = 0xc0;
398 +
399 + conf->step_size = ecc_cfg->step_size;
400 + conf->strength = ecc_cfg->strength;
401 +
402 + snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
403 + snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
404 +
405 + dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
406 + ecc_cfg->strength, ecc_cfg->step_size);
407 +
408 + return 0;
409 +}
410 +
411 +static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
412 +{
413 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
414 +
415 + kfree(ecc_cfg);
416 +}
417 +
418 +static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
419 + struct nand_page_io_req *req)
420 +{
421 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
422 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
423 +
424 + snandc->qspi->ecc = ecc_cfg;
425 + snandc->qspi->raw_rw = false;
426 + snandc->qspi->oob_rw = false;
427 + snandc->qspi->page_rw = false;
428 +
429 + if (req->datalen)
430 + snandc->qspi->page_rw = true;
431 +
432 + if (req->ooblen)
433 + snandc->qspi->oob_rw = true;
434 +
435 + if (req->mode == MTD_OPS_RAW)
436 + snandc->qspi->raw_rw = true;
437 +
438 + return 0;
439 +}
440 +
441 +static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
442 + struct nand_page_io_req *req)
443 +{
444 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
445 + struct mtd_info *mtd = nanddev_to_mtd(nand);
446 +
447 + if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
448 + return 0;
449 +
450 + if (snandc->qspi->ecc_stats.failed)
451 + mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
452 + else
453 + mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
454 +
455 + if (snandc->qspi->ecc_stats.failed)
456 + return -EBADMSG;
457 + else
458 + return snandc->qspi->ecc_stats.bitflips;
459 +}
460 +
461 +static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
462 + .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
463 + .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
464 + .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
465 + .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
466 +};
467 +
468 +/* helper to configure location register values */
469 +static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
470 + int cw_offset, int read_size, int is_last_read_loc)
471 +{
472 + int reg_base = NAND_READ_LOCATION_0;
473 + int num_cw = snandc->qspi->num_cw;
474 +
475 + if (cw == (num_cw - 1))
476 + reg_base = NAND_READ_LOCATION_LAST_CW_0;
477 +
478 + reg_base += reg * 4;
479 +
480 + if (cw == (num_cw - 1))
481 + return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
482 + read_size, is_last_read_loc);
483 + else
484 + return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
485 + read_size, is_last_read_loc);
486 +}
487 +
488 +static void
489 +qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
490 +{
491 + __le32 *reg = &snandc->regs->read_location0;
492 + int num_cw = snandc->qspi->num_cw;
493 +
494 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
495 + if (cw == (num_cw - 1)) {
496 + reg = &snandc->regs->read_location_last0;
497 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
498 + NAND_BAM_NEXT_SGL);
499 + }
500 +
501 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
502 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
503 +
504 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
505 + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
506 + NAND_BAM_NEXT_SGL);
507 +}
508 +
509 +static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
510 +{
511 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
512 + int ret;
513 +
514 + snandc->buf_count = 0;
515 + snandc->buf_start = 0;
516 + qcom_clear_read_regs(snandc);
517 + qcom_clear_bam_transaction(snandc);
518 +
519 + snandc->regs->cmd = snandc->qspi->cmd;
520 + snandc->regs->addr0 = snandc->qspi->addr1;
521 + snandc->regs->addr1 = snandc->qspi->addr2;
522 + snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE));
523 + snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
524 + snandc->regs->exec = cpu_to_le32(1);
525 +
526 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
527 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
528 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
529 +
530 + ret = qcom_submit_descs(snandc);
531 + if (ret) {
532 + dev_err(snandc->dev, "failure to erase block\n");
533 + return ret;
534 + }
535 +
536 + return 0;
537 +}
538 +
539 +static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
540 + bool use_ecc, int cw)
541 +{
542 + __le32 *reg = &snandc->regs->read_location0;
543 + int num_cw = snandc->qspi->num_cw;
544 +
545 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
546 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
547 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
548 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
549 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
550 + NAND_ERASED_CW_DETECT_CFG, 1,
551 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
552 +
553 + if (cw == (num_cw - 1)) {
554 + reg = &snandc->regs->read_location_last0;
555 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
556 + }
557 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
558 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
559 +
560 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
561 +}
562 +
563 +static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
564 + const struct spi_mem_op *op)
565 +{
566 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
567 + struct mtd_info *mtd = snandc->qspi->mtd;
568 + int size, ret = 0;
569 + int col, bbpos;
570 + u32 cfg0, cfg1, ecc_bch_cfg;
571 + u32 num_cw = snandc->qspi->num_cw;
572 +
573 + qcom_clear_bam_transaction(snandc);
574 + qcom_clear_read_regs(snandc);
575 +
576 + size = ecc_cfg->cw_size;
577 + col = ecc_cfg->cw_size * (num_cw - 1);
578 +
579 + memset(snandc->data_buffer, 0xff, size);
580 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
581 + snandc->regs->addr1 = snandc->qspi->addr2;
582 +
583 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
584 + 0 << CW_PER_PAGE;
585 + cfg1 = ecc_cfg->cfg1_raw;
586 + ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
587 +
588 + snandc->regs->cmd = snandc->qspi->cmd;
589 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
590 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
591 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
592 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
593 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
594 + snandc->regs->exec = cpu_to_le32(1);
595 +
596 + qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
597 +
598 + qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
599 +
600 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
601 +
602 + ret = qcom_submit_descs(snandc);
603 + if (ret) {
604 + dev_err(snandc->dev, "failed to read last cw\n");
605 + return ret;
606 + }
607 +
608 + qcom_nandc_dev_to_mem(snandc, true);
609 + u32 flash = le32_to_cpu(snandc->reg_read_buf[0]);
610 +
611 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
612 + return -EIO;
613 +
614 + bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
615 +
616 + if (snandc->data_buffer[bbpos] == 0xff)
617 + snandc->data_buffer[bbpos + 1] = 0xff;
618 + if (snandc->data_buffer[bbpos] != 0xff)
619 + snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
620 +
621 + memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
622 +
623 + return ret;
624 +}
625 +
626 +static int qcom_spi_check_error(struct qcom_nand_controller *snandc, u8 *data_buf, u8 *oob_buf)
627 +{
628 + struct snandc_read_status *buf;
629 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
630 + int i, num_cw = snandc->qspi->num_cw;
631 + bool flash_op_err = false, erased;
632 + unsigned int max_bitflips = 0;
633 + unsigned int uncorrectable_cws = 0;
634 +
635 + snandc->qspi->ecc_stats.failed = 0;
636 + snandc->qspi->ecc_stats.corrected = 0;
637 +
638 + qcom_nandc_dev_to_mem(snandc, true);
639 + buf = (struct snandc_read_status *)snandc->reg_read_buf;
640 +
641 + for (i = 0; i < num_cw; i++, buf++) {
642 + u32 flash, buffer, erased_cw;
643 + int data_len, oob_len;
644 +
645 + if (i == (num_cw - 1)) {
646 + data_len = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
647 + oob_len = num_cw << 2;
648 + } else {
649 + data_len = ecc_cfg->cw_data;
650 + oob_len = 0;
651 + }
652 +
653 + flash = le32_to_cpu(buf->snandc_flash);
654 + buffer = le32_to_cpu(buf->snandc_buffer);
655 + erased_cw = le32_to_cpu(buf->snandc_erased_cw);
656 +
657 + if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
658 + if (ecc_cfg->bch_enabled)
659 + erased = (erased_cw & ERASED_CW) == ERASED_CW;
660 + else
661 + erased = false;
662 +
663 + if (!erased)
664 + uncorrectable_cws |= BIT(i);
665 +
666 + } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
667 + flash_op_err = true;
668 + } else {
669 + unsigned int stat;
670 +
671 + stat = buffer & BS_CORRECTABLE_ERR_MSK;
672 + snandc->qspi->ecc_stats.corrected += stat;
673 + max_bitflips = max(max_bitflips, stat);
674 + }
675 +
676 + if (data_buf)
677 + data_buf += data_len;
678 + if (oob_buf)
679 + oob_buf += oob_len + ecc_cfg->bytes;
680 + }
681 +
682 + if (flash_op_err)
683 + return -EIO;
684 +
685 + if (!uncorrectable_cws)
686 + snandc->qspi->ecc_stats.bitflips = max_bitflips;
687 + else
688 + snandc->qspi->ecc_stats.failed++;
689 +
690 + return 0;
691 +}
692 +
693 +static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
694 +{
695 + int i;
696 +
697 + qcom_nandc_dev_to_mem(snandc, true);
698 +
699 + for (i = 0; i < cw_cnt; i++) {
700 + u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
701 +
702 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
703 + return -EIO;
704 + }
705 +
706 + return 0;
707 +}
708 +
709 +static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
710 + u8 *oob_buf, int cw)
711 +{
712 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
713 + struct mtd_info *mtd = snandc->qspi->mtd;
714 + int data_size1, data_size2, oob_size1, oob_size2;
715 + int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
716 + int raw_cw = cw;
717 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
718 + int col;
719 +
720 + snandc->buf_count = 0;
721 + snandc->buf_start = 0;
722 + qcom_clear_read_regs(snandc);
723 + qcom_clear_bam_transaction(snandc);
724 + raw_cw = num_cw - 1;
725 +
726 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
727 + 0 << CW_PER_PAGE;
728 + cfg1 = ecc_cfg->cfg1_raw;
729 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
730 +
731 + col = ecc_cfg->cw_size * cw;
732 +
733 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
734 + snandc->regs->addr1 = snandc->qspi->addr2;
735 + snandc->regs->cmd = snandc->qspi->cmd;
736 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
737 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
738 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
739 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
740 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
741 + snandc->regs->exec = cpu_to_le32(1);
742 +
743 + qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
744 +
745 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
746 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
747 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
748 +
749 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
750 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
751 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
752 + NAND_ERASED_CW_DETECT_CFG, 1,
753 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
754 +
755 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
756 + oob_size1 = ecc_cfg->bbm_size;
757 +
758 + if (cw == (num_cw - 1)) {
759 + data_size2 = NANDC_STEP_SIZE - data_size1 -
760 + ((num_cw - 1) * 4);
761 + oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
762 + ecc_cfg->spare_bytes;
763 + } else {
764 + data_size2 = ecc_cfg->cw_data - data_size1;
765 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
766 + }
767 +
768 + qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
769 + read_loc += data_size1;
770 +
771 + qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
772 + read_loc += oob_size1;
773 +
774 + qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
775 + read_loc += data_size2;
776 +
777 + qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
778 +
779 + qcom_spi_config_cw_read(snandc, false, raw_cw);
780 +
781 + qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
782 + reg_off += data_size1;
783 +
784 + qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
785 + reg_off += oob_size1;
786 +
787 + qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
788 + reg_off += data_size2;
789 +
790 + qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
791 +
792 + ret = qcom_submit_descs(snandc);
793 + if (ret) {
794 + dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
795 + return ret;
796 + }
797 +
798 + return qcom_spi_check_raw_flash_errors(snandc, 1);
799 +}
800 +
801 +static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
802 + const struct spi_mem_op *op)
803 +{
804 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
805 + u8 *data_buf = NULL, *oob_buf = NULL;
806 + int ret, cw;
807 + u32 num_cw = snandc->qspi->num_cw;
808 +
809 + if (snandc->qspi->page_rw)
810 + data_buf = op->data.buf.in;
811 +
812 + oob_buf = snandc->qspi->oob_buf;
813 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
814 +
815 + for (cw = 0; cw < num_cw; cw++) {
816 + ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
817 + if (ret)
818 + return ret;
819 +
820 + if (data_buf)
821 + data_buf += ecc_cfg->cw_data;
822 + if (oob_buf)
823 + oob_buf += ecc_cfg->bytes;
824 + }
825 +
826 + return 0;
827 +}
828 +
829 +static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
830 + const struct spi_mem_op *op)
831 +{
832 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
833 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
834 + int ret, i;
835 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
836 +
837 + data_buf = op->data.buf.in;
838 + data_buf_start = data_buf;
839 +
840 + oob_buf = snandc->qspi->oob_buf;
841 + oob_buf_start = oob_buf;
842 +
843 + snandc->buf_count = 0;
844 + snandc->buf_start = 0;
845 + qcom_clear_read_regs(snandc);
846 +
847 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
848 + (num_cw - 1) << CW_PER_PAGE;
849 + cfg1 = ecc_cfg->cfg1;
850 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
851 +
852 + snandc->regs->addr0 = snandc->qspi->addr1;
853 + snandc->regs->addr1 = snandc->qspi->addr2;
854 + snandc->regs->cmd = snandc->qspi->cmd;
855 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
856 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
857 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
858 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
859 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
860 + snandc->regs->exec = cpu_to_le32(1);
861 +
862 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
863 +
864 + qcom_clear_bam_transaction(snandc);
865 +
866 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
867 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
868 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
869 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
870 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
871 + NAND_ERASED_CW_DETECT_CFG, 1,
872 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
873 +
874 + for (i = 0; i < num_cw; i++) {
875 + int data_size, oob_size;
876 +
877 + if (i == (num_cw - 1)) {
878 + data_size = 512 - ((num_cw - 1) << 2);
879 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
880 + ecc_cfg->spare_bytes;
881 + } else {
882 + data_size = ecc_cfg->cw_data;
883 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
884 + }
885 +
886 + if (data_buf && oob_buf) {
887 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
888 + qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
889 + } else if (data_buf) {
890 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
891 + } else {
892 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
893 + }
894 +
895 + qcom_spi_config_cw_read(snandc, true, i);
896 +
897 + if (data_buf)
898 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
899 + data_size, 0);
900 + if (oob_buf) {
901 + int j;
902 +
903 + for (j = 0; j < ecc_cfg->bbm_size; j++)
904 + *oob_buf++ = 0xff;
905 +
906 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
907 + oob_buf, oob_size, 0);
908 + }
909 +
910 + if (data_buf)
911 + data_buf += data_size;
912 + if (oob_buf)
913 + oob_buf += oob_size;
914 + }
915 +
916 + ret = qcom_submit_descs(snandc);
917 + if (ret) {
918 + dev_err(snandc->dev, "failure to read page\n");
919 + return ret;
920 + }
921 +
922 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
923 +}
924 +
925 +static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
926 + const struct spi_mem_op *op)
927 +{
928 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
929 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
930 + int ret, i;
931 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
932 +
933 + oob_buf = op->data.buf.in;
934 + oob_buf_start = oob_buf;
935 +
936 + data_buf_start = data_buf;
937 +
938 + snandc->buf_count = 0;
939 + snandc->buf_start = 0;
940 + qcom_clear_read_regs(snandc);
941 + qcom_clear_bam_transaction(snandc);
942 +
943 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
944 + (num_cw - 1) << CW_PER_PAGE;
945 + cfg1 = ecc_cfg->cfg1;
946 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
947 +
948 + snandc->regs->addr0 = snandc->qspi->addr1;
949 + snandc->regs->addr1 = snandc->qspi->addr2;
950 + snandc->regs->cmd = snandc->qspi->cmd;
951 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
952 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
953 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
954 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
955 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
956 + snandc->regs->exec = cpu_to_le32(1);
957 +
958 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
959 +
960 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
961 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
962 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
963 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
964 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
965 + NAND_ERASED_CW_DETECT_CFG, 1,
966 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
967 +
968 + for (i = 0; i < num_cw; i++) {
969 + int data_size, oob_size;
970 +
971 + if (i == (num_cw - 1)) {
972 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
973 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
974 + ecc_cfg->spare_bytes;
975 + } else {
976 + data_size = ecc_cfg->cw_data;
977 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
978 + }
979 +
980 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
981 +
982 + qcom_spi_config_cw_read(snandc, true, i);
983 +
984 + if (oob_buf) {
985 + int j;
986 +
987 + for (j = 0; j < ecc_cfg->bbm_size; j++)
988 + *oob_buf++ = 0xff;
989 +
990 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
991 + oob_buf, oob_size, 0);
992 + }
993 +
994 + if (oob_buf)
995 + oob_buf += oob_size;
996 + }
997 +
998 + ret = qcom_submit_descs(snandc);
999 + if (ret) {
1000 + dev_err(snandc->dev, "failure to read oob\n");
1001 + return ret;
1002 + }
1003 +
1004 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
1005 +}
1006 +
1007 +static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
1008 + const struct spi_mem_op *op)
1009 +{
1010 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1011 + return qcom_spi_read_page_raw(snandc, op);
1012 +
1013 + if (snandc->qspi->page_rw)
1014 + return qcom_spi_read_page_ecc(snandc, op);
1015 +
1016 + if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
1017 + return qcom_spi_read_last_cw(snandc, op);
1018 +
1019 + if (snandc->qspi->oob_rw)
1020 + return qcom_spi_read_page_oob(snandc, op);
1021 +
1022 + return 0;
1023 +}
1024 +
1025 +static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
1026 +{
1027 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1028 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1029 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
1030 + 1, NAND_BAM_NEXT_SGL);
1031 +}
1032 +
1033 +static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1034 +{
1035 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1036 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1037 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1038 +
1039 + qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1040 + qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1041 + NAND_BAM_NEXT_SGL);
1042 +}
1043 +
1044 +static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1045 + const struct spi_mem_op *op)
1046 +{
1047 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1048 + struct mtd_info *mtd = snandc->qspi->mtd;
1049 + u8 *data_buf = NULL, *oob_buf = NULL;
1050 + int i, ret;
1051 + int num_cw = snandc->qspi->num_cw;
1052 + u32 cfg0, cfg1, ecc_bch_cfg;
1053 +
1054 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
1055 + (num_cw - 1) << CW_PER_PAGE;
1056 + cfg1 = ecc_cfg->cfg1_raw;
1057 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1058 +
1059 + data_buf = snandc->qspi->data_buf;
1060 +
1061 + oob_buf = snandc->qspi->oob_buf;
1062 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
1063 +
1064 + snandc->buf_count = 0;
1065 + snandc->buf_start = 0;
1066 + qcom_clear_read_regs(snandc);
1067 + qcom_clear_bam_transaction(snandc);
1068 +
1069 + snandc->regs->addr0 = snandc->qspi->addr1;
1070 + snandc->regs->addr1 = snandc->qspi->addr2;
1071 + snandc->regs->cmd = snandc->qspi->cmd;
1072 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1073 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1074 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1075 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1076 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1077 + snandc->regs->exec = cpu_to_le32(1);
1078 +
1079 + qcom_spi_config_page_write(snandc);
1080 +
1081 + for (i = 0; i < num_cw; i++) {
1082 + int data_size1, data_size2, oob_size1, oob_size2;
1083 + int reg_off = FLASH_BUF_ACC;
1084 +
1085 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1086 + oob_size1 = ecc_cfg->bbm_size;
1087 +
1088 + if (i == (num_cw - 1)) {
1089 + data_size2 = NANDC_STEP_SIZE - data_size1 -
1090 + ((num_cw - 1) << 2);
1091 + oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1092 + ecc_cfg->spare_bytes;
1093 + } else {
1094 + data_size2 = ecc_cfg->cw_data - data_size1;
1095 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1096 + }
1097 +
1098 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1099 + NAND_BAM_NO_EOT);
1100 + reg_off += data_size1;
1101 + data_buf += data_size1;
1102 +
1103 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1104 + NAND_BAM_NO_EOT);
1105 + oob_buf += oob_size1;
1106 + reg_off += oob_size1;
1107 +
1108 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1109 + NAND_BAM_NO_EOT);
1110 + reg_off += data_size2;
1111 + data_buf += data_size2;
1112 +
1113 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1114 + oob_buf += oob_size2;
1115 +
1116 + qcom_spi_config_cw_write(snandc);
1117 + }
1118 +
1119 + ret = qcom_submit_descs(snandc);
1120 + if (ret) {
1121 + dev_err(snandc->dev, "failure to write raw page\n");
1122 + return ret;
1123 + }
1124 +
1125 + return 0;
1126 +}
1127 +
1128 +static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1129 + const struct spi_mem_op *op)
1130 +{
1131 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1132 + u8 *data_buf = NULL, *oob_buf = NULL;
1133 + int i, ret;
1134 + int num_cw = snandc->qspi->num_cw;
1135 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1136 +
1137 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1138 + (num_cw - 1) << CW_PER_PAGE;
1139 + cfg1 = ecc_cfg->cfg1;
1140 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1141 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1142 +
1143 + if (snandc->qspi->data_buf)
1144 + data_buf = snandc->qspi->data_buf;
1145 +
1146 + oob_buf = snandc->qspi->oob_buf;
1147 +
1148 + snandc->buf_count = 0;
1149 + snandc->buf_start = 0;
1150 + qcom_clear_read_regs(snandc);
1151 + qcom_clear_bam_transaction(snandc);
1152 +
1153 + snandc->regs->addr0 = snandc->qspi->addr1;
1154 + snandc->regs->addr1 = snandc->qspi->addr2;
1155 + snandc->regs->cmd = snandc->qspi->cmd;
1156 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1157 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1158 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1159 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1160 + snandc->regs->exec = cpu_to_le32(1);
1161 +
1162 + qcom_spi_config_page_write(snandc);
1163 +
1164 + for (i = 0; i < num_cw; i++) {
1165 + int data_size, oob_size;
1166 +
1167 + if (i == (num_cw - 1)) {
1168 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1169 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1170 + ecc_cfg->spare_bytes;
1171 + } else {
1172 + data_size = ecc_cfg->cw_data;
1173 + oob_size = ecc_cfg->bytes;
1174 + }
1175 +
1176 + if (data_buf)
1177 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1178 + i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1179 +
1180 + if (i == (num_cw - 1)) {
1181 + if (oob_buf) {
1182 + oob_buf += ecc_cfg->bbm_size;
1183 + qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1184 + oob_buf, oob_size, 0);
1185 + }
1186 + }
1187 +
1188 + qcom_spi_config_cw_write(snandc);
1189 +
1190 + if (data_buf)
1191 + data_buf += data_size;
1192 + if (oob_buf)
1193 + oob_buf += oob_size;
1194 + }
1195 +
1196 + ret = qcom_submit_descs(snandc);
1197 + if (ret) {
1198 + dev_err(snandc->dev, "failure to write page\n");
1199 + return ret;
1200 + }
1201 +
1202 + return 0;
1203 +}
1204 +
1205 +static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1206 + const struct spi_mem_op *op)
1207 +{
1208 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1209 + u8 *oob_buf = NULL;
1210 + int ret, col, data_size, oob_size;
1211 + int num_cw = snandc->qspi->num_cw;
1212 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1213 +
1214 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1215 + (num_cw - 1) << CW_PER_PAGE;
1216 + cfg1 = ecc_cfg->cfg1;
1217 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1218 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1219 +
1220 + col = ecc_cfg->cw_size * (num_cw - 1);
1221 +
1222 + oob_buf = snandc->qspi->data_buf;
1223 +
1224 + snandc->buf_count = 0;
1225 + snandc->buf_start = 0;
1226 + qcom_clear_read_regs(snandc);
1227 + qcom_clear_bam_transaction(snandc);
1228 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1229 + snandc->regs->addr1 = snandc->qspi->addr2;
1230 + snandc->regs->cmd = snandc->qspi->cmd;
1231 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1232 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1233 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1234 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1235 + snandc->regs->exec = cpu_to_le32(1);
1236 +
1237 + /* calculate the data and oob size for the last codeword/step */
1238 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1239 + oob_size = snandc->qspi->mtd->oobavail;
1240 +
1241 + memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1242 + /* override new oob content to last codeword */
1243 + mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1244 + oob_buf, 0, snandc->qspi->mtd->oobavail);
1245 + qcom_spi_config_page_write(snandc);
1246 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1247 + qcom_spi_config_cw_write(snandc);
1248 +
1249 + ret = qcom_submit_descs(snandc);
1250 + if (ret) {
1251 + dev_err(snandc->dev, "failure to write oob\n");
1252 + return ret;
1253 + }
1254 +
1255 + return 0;
1256 +}
1257 +
1258 +static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1259 + const struct spi_mem_op *op)
1260 +{
1261 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1262 + return qcom_spi_program_raw(snandc, op);
1263 +
1264 + if (snandc->qspi->page_rw)
1265 + return qcom_spi_program_ecc(snandc, op);
1266 +
1267 + if (snandc->qspi->oob_rw)
1268 + return qcom_spi_program_oob(snandc, op);
1269 +
1270 + return 0;
1271 +}
1272 +
1273 +static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
1274 +{
1275 + switch (opcode) {
1276 + case SPINAND_RESET:
1277 + *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1278 + break;
1279 + case SPINAND_READID:
1280 + *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1281 + break;
1282 + case SPINAND_GET_FEATURE:
1283 + *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1284 + break;
1285 + case SPINAND_SET_FEATURE:
1286 + *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1287 + QPIC_SET_FEATURE);
1288 + break;
1289 + case SPINAND_READ:
1290 + if (snandc->qspi->raw_rw) {
1291 + *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1292 + SPI_WP | SPI_HOLD | OP_PAGE_READ);
1293 + } else {
1294 + *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1295 + SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1296 + }
1297 +
1298 + break;
1299 + case SPINAND_ERASE:
1300 + *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1301 + SPI_HOLD | SPI_TRANSFER_MODE_x1;
1302 + break;
1303 + case SPINAND_WRITE_EN:
1304 + *cmd = SPINAND_WRITE_EN;
1305 + break;
1306 + case SPINAND_PROGRAM_EXECUTE:
1307 + *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1308 + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1309 + break;
1310 + case SPINAND_PROGRAM_LOAD:
1311 + *cmd = SPINAND_PROGRAM_LOAD;
1312 + break;
1313 + default:
1314 + dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1315 + return -EOPNOTSUPP;
1316 + }
1317 +
1318 + return 0;
1319 +}
1320 +
1321 +static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1322 + const struct spi_mem_op *op)
1323 +{
1324 + int ret;
1325 + u32 cmd;
1326 +
1327 + ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1328 + if (ret < 0)
1329 + return ret;
1330 +
1331 + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1332 + snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1333 +
1334 + return 0;
1335 +}
1336 +
1337 +static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1338 + const struct spi_mem_op *op)
1339 +{
1340 + struct qpic_snand_op s_op = {};
1341 + u32 cmd;
1342 + int ret, opcode;
1343 +
1344 + ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
1345 + if (ret < 0)
1346 + return ret;
1347 +
1348 + s_op.cmd_reg = cmd;
1349 + s_op.addr1_reg = op->addr.val;
1350 + s_op.addr2_reg = 0;
1351 +
1352 + opcode = op->cmd.opcode;
1353 +
1354 + switch (opcode) {
1355 + case SPINAND_WRITE_EN:
1356 + return 0;
1357 + case SPINAND_PROGRAM_EXECUTE:
1358 + s_op.addr1_reg = op->addr.val << 16;
1359 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1360 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1361 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1362 + snandc->qspi->cmd = cpu_to_le32(cmd);
1363 + return qcom_spi_program_execute(snandc, op);
1364 + case SPINAND_READ:
1365 + s_op.addr1_reg = (op->addr.val << 16);
1366 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1367 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1368 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1369 + snandc->qspi->cmd = cpu_to_le32(cmd);
1370 + return 0;
1371 + case SPINAND_ERASE:
1372 + s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1373 + s_op.addr1_reg = op->addr.val;
1374 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1375 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1376 + snandc->qspi->cmd = cpu_to_le32(cmd);
1377 + qcom_spi_block_erase(snandc);
1378 + return 0;
1379 + default:
1380 + break;
1381 + }
1382 +
1383 + snandc->buf_count = 0;
1384 + snandc->buf_start = 0;
1385 + qcom_clear_read_regs(snandc);
1386 + qcom_clear_bam_transaction(snandc);
1387 +
1388 + snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1389 + snandc->regs->exec = cpu_to_le32(1);
1390 + snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1391 + snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1392 +
1393 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1394 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1395 +
1396 + ret = qcom_submit_descs(snandc);
1397 + if (ret)
1398 + dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1399 +
1400 + return ret;
1401 +}
1402 +
1403 +static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1404 +{
1405 + int ret, val, opcode;
1406 + bool copy = false, copy_ftr = false;
1407 +
1408 + ret = qcom_spi_send_cmdaddr(snandc, op);
1409 + if (ret)
1410 + return ret;
1411 +
1412 + snandc->buf_count = 0;
1413 + snandc->buf_start = 0;
1414 + qcom_clear_read_regs(snandc);
1415 + qcom_clear_bam_transaction(snandc);
1416 + opcode = op->cmd.opcode;
1417 +
1418 + switch (opcode) {
1419 + case SPINAND_READID:
1420 + snandc->buf_count = 4;
1421 + qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1422 + copy = true;
1423 + break;
1424 + case SPINAND_GET_FEATURE:
1425 + snandc->buf_count = 4;
1426 + qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1427 + copy_ftr = true;
1428 + break;
1429 + case SPINAND_SET_FEATURE:
1430 + snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1431 + qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1432 + NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1433 + break;
1434 + case SPINAND_PROGRAM_EXECUTE:
1435 + case SPINAND_WRITE_EN:
1436 + case SPINAND_RESET:
1437 + case SPINAND_ERASE:
1438 + case SPINAND_READ:
1439 + return 0;
1440 + default:
1441 + return -EOPNOTSUPP;
1442 + }
1443 +
1444 + ret = qcom_submit_descs(snandc);
1445 + if (ret)
1446 + dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1447 +
1448 + if (copy) {
1449 + qcom_nandc_dev_to_mem(snandc, true);
1450 + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1451 + }
1452 +
1453 + if (copy_ftr) {
1454 + qcom_nandc_dev_to_mem(snandc, true);
1455 + val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1456 + val >>= 8;
1457 + memcpy(op->data.buf.in, &val, snandc->buf_count);
1458 + }
1459 +
1460 + return ret;
1461 +}
1462 +
1463 +static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1464 +{
1465 + if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1466 + return false;
1467 +
1468 + if (op->data.dir == SPI_MEM_DATA_IN) {
1469 + if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1470 + return true;
1471 +
1472 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1473 + return true;
1474 +
1475 + } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1476 + if (op->data.buswidth == 4)
1477 + return true;
1478 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1479 + return true;
1480 + }
1481 +
1482 + return false;
1483 +}
1484 +
1485 +static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1486 +{
1487 + if (!spi_mem_default_supports_op(mem, op))
1488 + return false;
1489 +
1490 + if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1491 + return false;
1492 +
1493 + if (qcom_spi_is_page_op(op))
1494 + return true;
1495 +
1496 + return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1497 + (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1498 + (!op->data.nbytes || op->data.buswidth == 1));
1499 +}
1500 +
1501 +static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1502 +{
1503 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1504 +
1505 + dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1506 + op->addr.val, op->addr.buswidth, op->addr.nbytes,
1507 + op->data.buswidth, op->data.nbytes);
1508 +
1509 + if (qcom_spi_is_page_op(op)) {
1510 + if (op->data.dir == SPI_MEM_DATA_IN)
1511 + return qcom_spi_read_page(snandc, op);
1512 + if (op->data.dir == SPI_MEM_DATA_OUT)
1513 + return qcom_spi_write_page(snandc, op);
1514 + } else {
1515 + return qcom_spi_io_op(snandc, op);
1516 + }
1517 +
1518 + return 0;
1519 +}
1520 +
1521 +static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1522 + .supports_op = qcom_spi_supports_op,
1523 + .exec_op = qcom_spi_exec_op,
1524 +};
1525 +
1526 +static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1527 + .ecc = true,
1528 +};
1529 +
1530 +static int qcom_spi_probe(struct platform_device *pdev)
1531 +{
1532 + struct device *dev = &pdev->dev;
1533 + struct spi_controller *ctlr;
1534 + struct qcom_nand_controller *snandc;
1535 + struct qpic_spi_nand *qspi;
1536 + struct qpic_ecc *ecc;
1537 + struct resource *res;
1538 + const void *dev_data;
1539 + int ret;
1540 +
1541 + ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1542 + if (!ecc)
1543 + return -ENOMEM;
1544 +
1545 + qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1546 + if (!qspi)
1547 + return -ENOMEM;
1548 +
1549 + ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1550 + if (!ctlr)
1551 + return -ENOMEM;
1552 +
1553 + platform_set_drvdata(pdev, ctlr);
1554 +
1555 + snandc = spi_controller_get_devdata(ctlr);
1556 + qspi->snandc = snandc;
1557 +
1558 + snandc->dev = dev;
1559 + snandc->qspi = qspi;
1560 + snandc->qspi->ctlr = ctlr;
1561 + snandc->qspi->ecc = ecc;
1562 +
1563 + dev_data = of_device_get_match_data(dev);
1564 + if (!dev_data) {
1565 + dev_err(&pdev->dev, "failed to get device data\n");
1566 + return -ENODEV;
1567 + }
1568 +
1569 + snandc->props = dev_data;
1570 + snandc->dev = &pdev->dev;
1571 +
1572 + snandc->core_clk = devm_clk_get(dev, "core");
1573 + if (IS_ERR(snandc->core_clk))
1574 + return PTR_ERR(snandc->core_clk);
1575 +
1576 + snandc->aon_clk = devm_clk_get(dev, "aon");
1577 + if (IS_ERR(snandc->aon_clk))
1578 + return PTR_ERR(snandc->aon_clk);
1579 +
1580 + snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom");
1581 + if (IS_ERR(snandc->qspi->iomacro_clk))
1582 + return PTR_ERR(snandc->qspi->iomacro_clk);
1583 +
1584 + snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1585 + if (IS_ERR(snandc->base))
1586 + return PTR_ERR(snandc->base);
1587 +
1588 + snandc->base_phys = res->start;
1589 + snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1590 + DMA_BIDIRECTIONAL, 0);
1591 + if (dma_mapping_error(dev, snandc->base_dma))
1592 + return -ENXIO;
1593 +
1594 + ret = clk_prepare_enable(snandc->core_clk);
1595 + if (ret)
1596 + goto err_dis_core_clk;
1597 +
1598 + ret = clk_prepare_enable(snandc->aon_clk);
1599 + if (ret)
1600 + goto err_dis_aon_clk;
1601 +
1602 + ret = clk_prepare_enable(snandc->qspi->iomacro_clk);
1603 + if (ret)
1604 + goto err_dis_iom_clk;
1605 +
1606 + ret = qcom_nandc_alloc(snandc);
1607 + if (ret)
1608 + goto err_snand_alloc;
1609 +
1610 + ret = qcom_spi_init(snandc);
1611 + if (ret)
1612 + goto err_spi_init;
1613 +
1614 + /* setup ECC engine */
1615 + snandc->qspi->ecc_eng.dev = &pdev->dev;
1616 + snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1617 + snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1618 + snandc->qspi->ecc_eng.priv = snandc;
1619 +
1620 + ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1621 + if (ret) {
1622 + dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1623 + goto err_spi_init;
1624 + }
1625 +
1626 + ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1627 + ctlr->mem_ops = &qcom_spi_mem_ops;
1628 + ctlr->mem_caps = &qcom_spi_mem_caps;
1629 + ctlr->dev.of_node = pdev->dev.of_node;
1630 + ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1631 + SPI_TX_QUAD | SPI_RX_QUAD;
1632 +
1633 + ret = spi_register_controller(ctlr);
1634 + if (ret) {
1635 + dev_err(&pdev->dev, "spi_register_controller failed.\n");
1636 + goto err_spi_init;
1637 + }
1638 +
1639 + return 0;
1640 +
1641 +err_spi_init:
1642 + qcom_nandc_unalloc(snandc);
1643 +err_snand_alloc:
1644 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1645 +err_dis_iom_clk:
1646 + clk_disable_unprepare(snandc->aon_clk);
1647 +err_dis_aon_clk:
1648 + clk_disable_unprepare(snandc->core_clk);
1649 +err_dis_core_clk:
1650 + dma_unmap_resource(dev, res->start, resource_size(res),
1651 + DMA_BIDIRECTIONAL, 0);
1652 + return ret;
1653 +}
1654 +
1655 +static void qcom_spi_remove(struct platform_device *pdev)
1656 +{
1657 + struct spi_controller *ctlr = platform_get_drvdata(pdev);
1658 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1659 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1660 +
1661 + spi_unregister_controller(ctlr);
1662 +
1663 + qcom_nandc_unalloc(snandc);
1664 +
1665 + clk_disable_unprepare(snandc->aon_clk);
1666 + clk_disable_unprepare(snandc->core_clk);
1667 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1668 +
1669 + dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1670 + DMA_BIDIRECTIONAL, 0);
1671 +}
1672 +
1673 +static const struct qcom_nandc_props ipq9574_snandc_props = {
1674 + .dev_cmd_reg_start = 0x7000,
1675 + .supports_bam = true,
1676 +};
1677 +
1678 +static const struct of_device_id qcom_snandc_of_match[] = {
1679 + {
1680 + .compatible = "qcom,ipq9574-snand",
1681 + .data = &ipq9574_snandc_props,
1682 + },
1683 + {}
1684 +}
1685 +MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1686 +
1687 +static struct platform_driver qcom_spi_driver = {
1688 + .driver = {
1689 + .name = "qcom_snand",
1690 + .of_match_table = qcom_snandc_of_match,
1691 + },
1692 + .probe = qcom_spi_probe,
1693 + .remove_new = qcom_spi_remove,
1694 +};
1695 +module_platform_driver(qcom_spi_driver);
1696 +
1697 +MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1698 +MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1699 +MODULE_LICENSE("GPL");
1700 +
1701 --- a/include/linux/mtd/nand-qpic-common.h
1702 +++ b/include/linux/mtd/nand-qpic-common.h
1703 @@ -325,6 +325,10 @@ struct nandc_regs {
1704 __le32 read_location_last1;
1705 __le32 read_location_last2;
1706 __le32 read_location_last3;
1707 + __le32 spi_cfg;
1708 + __le32 num_addr_cycle;
1709 + __le32 busy_wait_cnt;
1710 + __le32 flash_feature;
1711
1712 __le32 erased_cw_detect_cfg_clr;
1713 __le32 erased_cw_detect_cfg_set;
1714 @@ -339,6 +343,7 @@ struct nandc_regs {
1715 *
1716 * @core_clk: controller clock
1717 * @aon_clk: another controller clock
1718 + * @iomacro_clk: io macro clock
1719 *
1720 * @regs: a contiguous chunk of memory for DMA register
1721 * writes. contains the register values to be
1722 @@ -348,6 +353,7 @@ struct nandc_regs {
1723 * initialized via DT match data
1724 *
1725 * @controller: base controller structure
1726 + * @qspi: qpic spi structure
1727 * @host_list: list containing all the chips attached to the
1728 * controller
1729 *
1730 @@ -392,6 +398,7 @@ struct qcom_nand_controller {
1731 const struct qcom_nandc_props *props;
1732
1733 struct nand_controller *controller;
1734 + struct qpic_spi_nand *qspi;
1735 struct list_head host_list;
1736
1737 union {
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