git.openwrt.org Git - openwrt/staging/linusw.git/blob

   1 From bbb70265fd52ea75bd59c6d23632418dd905bad1 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Fri, 22 Mar 2024 14:41:07 +0000
   4 Subject: [PATCH 0987/1085] ARM: dts: bcm2712: Add the missing L1/L2/L3 cache
   5  information
   6
   7 This provides the missing cache information for bcm2712
   8
   9 lscpu now reports:
  10
  11 Caches (sum of all):
  12   L1d:                    256 KiB (4 instances)
  13   L1i:                    256 KiB (4 instances)
  14   L2:                     2 MiB (4 instances)
  15   L3:                     2 MiB (1 instance)
  16
  17 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  18 ---
  19  arch/arm/boot/dts/broadcom/bcm2712.dtsi | 89 +++++++++++++++++++++++--
  20  1 file changed, 84 insertions(+), 5 deletions(-)
  21
  22 --- a/arch/arm/boot/dts/broadcom/bcm2712.dtsi
  23 +++ b/arch/arm/boot/dts/broadcom/bcm2712.dtsi
  24 @@ -750,12 +750,22 @@
  25                 #size-cells = <0>;
  26                 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
  27
  28 +               /* Source for d/i cache-line-size, cache-sets, cache-size
  29 +                * https://developer.arm.com/documentation/100798/0401
  30 +                * /L1-memory-system/About-the-L1-memory-system?lang=en
  31 +                */
  32                 cpu0: cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a76";
  35                         reg = <0x000>;
  36                         enable-method = "psci";
  37 -                       next-level-cache = <&l2_cache>;
  38 +                       d-cache-size = <0x10000>;
  39 +                       d-cache-line-size = <64>;
  40 +                       d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  41 +                       i-cache-size = <0x10000>;
  42 +                       i-cache-line-size = <64>;
  43 +                       i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  44 +                       next-level-cache = <&l2_cache_l0>;
  45                 };
  46
  47                 cpu1: cpu@1 {
  48 @@ -763,7 +773,13 @@
  49                         compatible = "arm,cortex-a76";
  50                         reg = <0x100>;
  51                         enable-method = "psci";
  52 -                       next-level-cache = <&l2_cache>;
  53 +                       d-cache-size = <0x10000>;
  54 +                       d-cache-line-size = <64>;
  55 +                       d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  56 +                       i-cache-size = <0x10000>;
  57 +                       i-cache-line-size = <64>;
  58 +                       i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  59 +                       next-level-cache = <&l2_cache_l1>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63 @@ -771,7 +787,13 @@
  64                         compatible = "arm,cortex-a76";
  65                         reg = <0x200>;
  66                         enable-method = "psci";
  67 -                       next-level-cache = <&l2_cache>;
  68 +                       d-cache-size = <0x10000>;
  69 +                       d-cache-line-size = <64>;
  70 +                       d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  71 +                       i-cache-size = <0x10000>;
  72 +                       i-cache-line-size = <64>;
  73 +                       i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  74 +                       next-level-cache = <&l2_cache_l2>;
  75                 };
  76
  77                 cpu3: cpu@3 {
  78 @@ -779,16 +801,73 @@
  79                         compatible = "arm,cortex-a76";
  80                         reg = <0x300>;
  81                         enable-method = "psci";
  82 -                       next-level-cache = <&l2_cache>;
  83 +                       d-cache-size = <0x10000>;
  84 +                       d-cache-line-size = <64>;
  85 +                       d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  86 +                       i-cache-size = <0x10000>;
  87 +                       i-cache-line-size = <64>;
  88 +                       i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
  89 +                       next-level-cache = <&l2_cache_l3>;
  90 +               };
  91 +
  92 +               /* Source for cache-line-size and cache-sets:
  93 +                * https://developer.arm.com/documentation/100798/0401
  94 +                * /L2-memory-system/About-the-L2-memory-system?lang=en
  95 +                * and for cache-size:
  96 +                * https://www.raspberrypi.com/documentation/computers
  97 +                * /processors.html#bcm2712
  98 +                */
  99 +               l2_cache_l0: l2-cache-l0 {
 100 +                       compatible = "cache";
 101 +                       cache-size = <0x80000>;
 102 +                       cache-line-size = <128>;
 103 +                       cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
 104 +                       cache-level = <2>;
 105 +                       cache-unified;
 106 +                       next-level-cache = <&l3_cache>;
 107 +               };
 108 +
 109 +               l2_cache_l1: l2-cache-l1 {
 110 +                       compatible = "cache";
 111 +                       cache-size = <0x80000>;
 112 +                       cache-line-size = <128>;
 113 +                       cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
 114 +                       cache-level = <2>;
 115 +                       cache-unified;
 116 +                       next-level-cache = <&l3_cache>;
 117 +               };
 118 +
 119 +               l2_cache_l2: l2-cache-l2 {
 120 +                       compatible = "cache";
 121 +                       cache-size = <0x80000>;
 122 +                       cache-line-size = <128>;
 123 +                       cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
 124 +                       cache-level = <2>;
 125 +                       cache-unified;
 126 +                       next-level-cache = <&l3_cache>;
 127                 };
 128
 129 -               l2_cache: l2-cache {
 130 +               l2_cache_l3: l2-cache-l3 {
 131                         compatible = "cache";
 132 +                       cache-size = <0x80000>;
 133 +                       cache-line-size = <128>;
 134 +                       cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
 135 +                       cache-level = <2>;
 136 +                       cache-unified;
 137                         next-level-cache = <&l3_cache>;
 138                 };
 139
 140 +               /* Source for cache-line-size and cache-sets:
 141 +                * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
 142 +                * Source for cache-size:
 143 +                * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
 144 +                */
 145                 l3_cache: l3-cache {
 146                         compatible = "cache";
 147 +                       cache-size = <0x200000>;
 148 +                       cache-line-size = <64>;
 149 +                       cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
 150 +                       cache-level = <3>;
 151                 };
 152         };
 153