git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From bc1bb265f504ea19ce611a1aec1a40dec409cd15 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Wed, 18 Sep 2024 15:32:55 +0200
   4 Subject: [PATCH 4/4] phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions
   5
   6 Fix the following register definitions for REG_CSR_2L_RX{0,1}_REV0
   7 registers:
   8 - CSR_2L_PXP_VOS_PNINV
   9 - CSR_2L_PXP_FE_GAIN_NORMAL_MODE
  10 - CSR_2L_PXP_FE_GAIN_TRAIN_MODE
  11
  12 Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
  13 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  14 ---
  15  drivers/phy/phy-airoha-pcie-regs.h | 6 +++---
  16  1 file changed, 3 insertions(+), 3 deletions(-)
  17
  18 --- a/drivers/phy/phy-airoha-pcie-regs.h
  19 +++ b/drivers/phy/phy-airoha-pcie-regs.h
  20 @@ -197,9 +197,9 @@
  21  #define CSR_2L_PXP_TX1_MULTLANE_EN             BIT(0)
  22
  23  #define REG_CSR_2L_RX0_REV0                    0x00fc
  24 -#define CSR_2L_PXP_VOS_PNINV                   GENMASK(3, 2)
  25 -#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE         GENMASK(6, 4)
  26 -#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE          GENMASK(10, 8)
  27 +#define CSR_2L_PXP_VOS_PNINV                   GENMASK(19, 18)
  28 +#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE         GENMASK(22, 20)
  29 +#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE          GENMASK(26, 24)
  30
  31  #define REG_CSR_2L_RX0_PHYCK_DIV               0x0100
  32  #define CSR_2L_PXP_RX0_PHYCK_SEL               GENMASK(9, 8)