git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From ae682f13d308682232069e5150e884fc10160598 Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Mon, 29 Jan 2024 17:57:20 +0800
   4 Subject: [PATCH] dt-bindings: net: Document Qualcomm QCA8084 PHY package
   5
   6 QCA8084 is quad PHY chip, which integrates 4 PHYs, 2 PCS
   7 interfaces (PCS0 and PCS1) and clock controller, which can
   8 also be integrated to the switch chip named as QCA8386.
   9
  10 1. MDIO address of 4 PHYs, 2 PCS and 1 XPCS (PCS1 includes
  11    PCS and XPCS, PCS0 includes PCS) can be configured.
  12 2. The package mode of PHY is optionally configured for the
  13    interface mode of two PCSes working correctly.
  14 3. The package level clock and reset need to be initialized.
  15 4. The clock and reset per PHY device need to be initialized
  16    so that the PHY register can be accessed.
  17
  18 Change-Id: Idb2338d2673152cbd3c57e95968faa59e9d4a80f
  19 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  20 ---
  21  .../devicetree/bindings/net/qcom,qca8084.yaml | 198 ++++++++++++++++++
  22  include/dt-bindings/net/qcom,qca808x.h        |  14 ++
  23  2 files changed, 212 insertions(+)
  24  create mode 100644 Documentation/devicetree/bindings/net/qcom,qca8084.yaml
  25  create mode 100644 include/dt-bindings/net/qcom,qca808x.h
  26
  27 --- /dev/null
  28 +++ b/Documentation/devicetree/bindings/net/qcom,qca8084.yaml
  29 @@ -0,0 +1,198 @@
  30 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  31 +%YAML 1.2
  32 +---
  33 +$id: http://devicetree.org/schemas/net/qcom,qca8084.yaml#
  34 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  35 +
  36 +title: Qualcomm QCA8084 Ethernet Quad PHY
  37 +
  38 +maintainers:
  39 +  - Luo Jie <quic_luoj@quicinc.com>
  40 +
  41 +description:
  42 +  Qualcomm QCA8084 is a four-port Ethernet transceiver, the
  43 +  Ethernet port supports link speed 10/100/1000/2500 Mbps.
  44 +  There are two PCSes (PCS0 and PCS1) integrated in the PHY
  45 +  package, PCS1 includes XPCS and PCS to support the interface
  46 +  mode 10G-QXGMII and SGMII, PCS0 includes a PCS to support the
  47 +  interface mode SGMII only. There is also a clock controller
  48 +  integrated in the PHY package. This four-port Ethernet
  49 +  transceiver can also be integrated to the switch chip named
  50 +  as QCA8386. The PHY package mode needs to be configured as the
  51 +  correct value to apply the interface mode of two PCSes as
  52 +  mentioned below.
  53 +
  54 +  QCA8084 expects an input reference clock 50 MHZ as the clock
  55 +  source of the integrated clock controller, the integrated
  56 +  clock controller supplies the clocks and resets to the
  57 +  integrated PHY, PCS and PHY package.
  58 +
  59 +  - |
  60 +                 +--| |--+-------------------+--| |--+
  61 +                 | PCS1  |<------------+---->| PCS0  |
  62 +                 +-------+             |     +-------+
  63 +                 |                     |             |
  64 +    Ref 50M clk  +--------+            |             |
  65 +    ------------>|        | clk & rst  |             |
  66 +    GPIO Reset   |QCA8K_CC+------------+             |
  67 +    ------------>|        |            |             |
  68 +                 +--------+            |             |
  69 +                 |                     V             |
  70 +                 +--------+--------+--------+--------+
  71 +                 |  PHY0  |  PHY1  |  PHY2  |  PHY3  |
  72 +                 +--------+--------+--------+--------+
  73 +
  74 +$ref: ethernet-phy-package.yaml#
  75 +
  76 +properties:
  77 +  compatible:
  78 +    const: qcom,qca8084-package
  79 +
  80 +  clocks:
  81 +    description: PHY package level initial common clocks, which are
  82 +      needed to be enabled after GPIO reset on the PHY package, these
  83 +      clocks are supplied from the PHY integrated clock controller
  84 +      (QCA8K-CC).
  85 +    items:
  86 +      - description: APB bridge clock
  87 +      - description: AHB clock
  88 +      - description: Security control clock
  89 +      - description: TLMM clock
  90 +      - description: TLMM AHB clock
  91 +      - description: CNOC AHB clock
  92 +      - description: MDIO AHB clock
  93 +
  94 +  clock-names:
  95 +    items:
  96 +      - const: apb_bridge
  97 +      - const: ahb
  98 +      - const: sec_ctrl_ahb
  99 +      - const: tlmm
 100 +      - const: tlmm_ahb
 101 +      - const: cnoc_ahb
 102 +      - const: mdio_ahb
 103 +
 104 +  resets:
 105 +    description: PHY package level initial common reset, which are
 106 +      needed to be deasserted after GPIO reset on the PHY package,
 107 +      this reset is provided by the PHY integrated clock controller
 108 +      to do PHY DSP reset.
 109 +    maxItems: 1
 110 +
 111 +  qcom,package-mode:
 112 +    description: |
 113 +      The package mode of PHY supports to be configured as 3 modes
 114 +      to apply the combinations of interface mode of two PCSes
 115 +      correctly. This value should use one of the values defined in
 116 +      dt-bindings/net/qcom,qca808x.h. The package mode 10G-QXGMII of
 117 +      Quad PHY is used by default.
 118 +
 119 +      package mode             PCS1             PCS0
 120 +      phy mode (0)             10G-QXGMII for   not used
 121 +                               PHY0-PHY3
 122 +
 123 +      switch mode (1)          SGMII for        SGMII for
 124 +                               switch MAC0      switch MAC5 (optional)
 125 +
 126 +      switch bypass MAC5 (2)   SGMII for        SGMII for
 127 +                               switch MAC0      PHY3
 128 +    $ref: /schemas/types.yaml#/definitions/uint32
 129 +    enum: [0, 1, 2]
 130 +    default: 0
 131 +
 132 +  qcom,phy-addr-fixup:
 133 +    description: MDIO address for PHY0-PHY3, PCS0 and PCS1 including
 134 +      PCS and XPCS, which can be optionally customized by programming
 135 +      the security control register of PHY package. The hardware default
 136 +      MDIO address of PHY0-PHY3, PCS0 and PCS1 including PCS and XPCS is
 137 +      0-6.
 138 +    $ref: /schemas/types.yaml#/definitions/uint32-array
 139 +    minItems: 7
 140 +    maxItems: 7
 141 +
 142 +patternProperties:
 143 +  ^ethernet-phy(@[a-f0-9]+)?$:
 144 +    $ref: ethernet-phy.yaml#
 145 +
 146 +    properties:
 147 +      compatible:
 148 +        const: ethernet-phy-id004d.d180
 149 +
 150 +    required:
 151 +      - compatible
 152 +      - reg
 153 +      - clocks
 154 +      - resets
 155 +
 156 +    unevaluatedProperties: false
 157 +
 158 +required:
 159 +  - compatible
 160 +  - clocks
 161 +  - clock-names
 162 +  - resets
 163 +
 164 +unevaluatedProperties: false
 165 +
 166 +examples:
 167 +  - |
 168 +    #include <dt-bindings/clock/qcom,qca8k-nsscc.h>
 169 +    #include <dt-bindings/net/qcom,qca808x.h>
 170 +    #include <dt-bindings/reset/qcom,qca8k-nsscc.h>
 171 +
 172 +    mdio {
 173 +        #address-cells = <1>;
 174 +        #size-cells = <0>;
 175 +
 176 +        ethernet-phy-package@1 {
 177 +            #address-cells = <1>;
 178 +            #size-cells = <0>;
 179 +            compatible = "qcom,qca8084-package";
 180 +            reg = <1>;
 181 +            clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
 182 +                     <&qca8k_nsscc NSS_CC_AHB_CLK>,
 183 +                     <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
 184 +                     <&qca8k_nsscc NSS_CC_TLMM_CLK>,
 185 +                     <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
 186 +                     <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
 187 +                     <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>;
 188 +            clock-names = "apb_bridge",
 189 +                          "ahb",
 190 +                          "sec_ctrl_ahb",
 191 +                          "tlmm",
 192 +                          "tlmm_ahb",
 193 +                          "cnoc_ahb",
 194 +                          "mdio_ahb";
 195 +            resets = <&qca8k_nsscc NSS_CC_GEPHY_FULL_ARES>;
 196 +            qcom,package-mode = <QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC>;
 197 +            qcom,phy-addr-fixup = <1 2 3 4 5 6 7>;
 198 +
 199 +            ethernet-phy@1 {
 200 +                compatible = "ethernet-phy-id004d.d180";
 201 +                reg = <1>;
 202 +                clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>;
 203 +                resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>;
 204 +            };
 205 +
 206 +            ethernet-phy@2 {
 207 +                compatible = "ethernet-phy-id004d.d180";
 208 +                reg = <2>;
 209 +                clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>;
 210 +                resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>;
 211 +            };
 212 +
 213 +            ethernet-phy@3 {
 214 +                compatible = "ethernet-phy-id004d.d180";
 215 +                reg = <3>;
 216 +                clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>;
 217 +                resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>;
 218 +            };
 219 +
 220 +            ethernet-phy@4 {
 221 +                compatible = "ethernet-phy-id004d.d180";
 222 +                reg = <4>;
 223 +                clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>;
 224 +                resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>;
 225 +            };
 226 +        };
 227 +    };
 228 --- /dev/null
 229 +++ b/include/dt-bindings/net/qcom,qca808x.h
 230 @@ -0,0 +1,14 @@
 231 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 232 +/*
 233 + * Device Tree constants for the Qualcomm QCA808X PHYs
 234 + */
 235 +
 236 +#ifndef _DT_BINDINGS_QCOM_QCA808X_H
 237 +#define _DT_BINDINGS_QCOM_QCA808X_H
 238 +
 239 +/* PHY package modes of QCA8084 to apply the interface modes of two PCSes. */
 240 +#define QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED           0
 241 +#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC          1
 242 +#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_PHY          2
 243 +
 244 +#endif