14f9dd8d8472a02905778a0bd47f60dd0494e83c
[openwrt/staging/linusw.git] /
1 From d62184f6b06627b4fe922b08132e38c181d389a0 Mon Sep 17 00:00:00 2001
2 From: Jagan Teki <jagan@amarulasolutions.com>
3 Date: Tue, 28 Mar 2023 22:37:52 +0530
4 Subject: [PATCH 1270/1350] drm/bridge: Document bridge init order with
5 pre_enable_prev_first
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 Upstream commit 113cc3ad8566e06d6c8ef4fc0075a938dedefab5
11
12 In order to satisfy the MIPI DSI initialization sequence the bridge
13 init order has been altered with the help of pre_enable_prev_first
14 in pre_enable and post_disable bridge operations.
15
16 Document the affected bridge init order with an example on the
17 bridge operations helpers.
18
19 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
20 Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
21 Signed-off-by: Robert Foss <rfoss@kernel.org>
22 Link: https://patchwork.freedesktop.org/patch/msgid/20230328170752.1102347-2-jagan@amarulasolutions.com
23 ---
24 drivers/gpu/drm/drm_bridge.c | 14 ++++++++++++++
25 1 file changed, 14 insertions(+)
26
27 --- a/drivers/gpu/drm/drm_bridge.c
28 +++ b/drivers/gpu/drm/drm_bridge.c
29 @@ -657,6 +657,13 @@ static void drm_atomic_bridge_call_post_
30 * bridge will be called before the previous one to reverse the @pre_enable
31 * calling direction.
32 *
33 + * Example:
34 + * Bridge A ---> Bridge B ---> Bridge C ---> Bridge D ---> Bridge E
35 + *
36 + * With pre_enable_prev_first flag enable in Bridge B, D, E then the resulting
37 + * @post_disable order would be,
38 + * Bridge B, Bridge A, Bridge E, Bridge D, Bridge C.
39 + *
40 * Note: the bridge passed should be the one closest to the encoder
41 */
42 void drm_atomic_bridge_chain_post_disable(struct drm_bridge *bridge,
43 @@ -753,6 +760,13 @@ static void drm_atomic_bridge_call_pre_e
44 * If a bridge sets @pre_enable_prev_first, then the pre_enable for the
45 * prev bridge will be called before pre_enable of this bridge.
46 *
47 + * Example:
48 + * Bridge A ---> Bridge B ---> Bridge C ---> Bridge D ---> Bridge E
49 + *
50 + * With pre_enable_prev_first flag enable in Bridge B, D, E then the resulting
51 + * @pre_enable order would be,
52 + * Bridge C, Bridge D, Bridge E, Bridge A, Bridge B.
53 + *
54 * Note: the bridge passed should be the one closest to the encoder
55 */
56 void drm_atomic_bridge_chain_pre_enable(struct drm_bridge *bridge,