git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From 33b561eb66f1e271f2899e103c857d20425076f4 Mon Sep 17 00:00:00 2001
   2 From: Dragan Simic <dsimic@manjaro.org>
   3 Date: Wed, 8 Jan 2025 05:26:45 +0100
   4 Subject: arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
   5
   6 The preferred way to denote hardware with non-coherent DMA is to use the
   7 "dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS
   8 levels, [1] instead of relying on the compatibles to handle hardware errata,
   9 in this case the Rockchip 3588001 errata. [2]
  10
  11 Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi,
  12 which also goes along with adding initial support for the Rockchip RK3582 SoC
  13 variant, with its separate compatible. [2][3]
  14
  15 [1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
  16 [2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/
  17 [3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/
  18
  19 Cc: Marc Zyngier <maz@kernel.org>
  20 Cc: FUKAUMI Naoki <naoki@radxa.com>
  21 Acked-by: Marc Zyngier <maz@kernel.org>
  22 Signed-off-by: Dragan Simic <dsimic@manjaro.org>
  23 Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org
  24 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  25
  26 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  27 +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
  28 @@ -2020,6 +2020,7 @@
  29                       <0x0 0xfe680000 0 0x100000>; /* GICR */
  30                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
  31                 interrupt-controller;
  32 +               dma-noncoherent;
  33                 mbi-alias = <0x0 0xfe610000>;
  34                 mbi-ranges = <424 56>;
  35                 msi-controller;
  36 @@ -2031,6 +2032,7 @@
  37                 its0: msi-controller@fe640000 {
  38                         compatible = "arm,gic-v3-its";
  39                         reg = <0x0 0xfe640000 0x0 0x20000>;
  40 +                       dma-noncoherent;
  41                         msi-controller;
  42                         #msi-cells = <1>;
  43                 };
  44 @@ -2038,6 +2040,7 @@
  45                 its1: msi-controller@fe660000 {
  46                         compatible = "arm,gic-v3-its";
  47                         reg = <0x0 0xfe660000 0x0 0x20000>;
  48 +                       dma-noncoherent;
  49                         msi-controller;
  50                         #msi-cells = <1>;
  51                 };