git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 217fbbc122663c5a3dac752cebef44fb3e0cc179 Mon Sep 17 00:00:00 2001
   2 From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
   3 Date: Fri, 10 Nov 2023 14:49:35 +0530
   4 Subject: [PATCH] firmware: qcom_scm: ipq5332: add msa lock/unlock
   5  support
   6
   7 IPQ5332 user pd remoteproc firmwares need to be locked
   8 with MSA(modem secure access) features. This patch add
   9 support to lock/unlock MSA features.
  10
  11 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
  12 ---
  13  drivers/firmware/qcom//qcom_scm.c            | 78 ++++++++++++++++++++++++++
  14  drivers/firmware/qcom//qcom_scm.h            |  2 +
  15  include/linux/firmware/qcom/qcom_scm.h |  2 +
  16  3 files changed, 82 insertions(+)
  17
  18 --- a/include/linux/firmware/qcom/qcom_scm.h
  19 +++ b/include/linux/firmware/qcom/qcom_scm.h
  20 @@ -79,6 +79,8 @@ int qcom_scm_pas_mem_setup(u32 periphera
  21  int qcom_scm_pas_auth_and_reset(u32 peripheral);
  22  int qcom_scm_pas_shutdown(u32 peripheral);
  23  bool qcom_scm_pas_supported(u32 peripheral);
  24 +int qcom_scm_msa_lock(u32 peripheral);
  25 +int qcom_scm_msa_unlock(u32 peripheral);
  26
  27  int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
  28  int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
  29 --- a/drivers/firmware/qcom/qcom_scm.c
  30 +++ b/drivers/firmware/qcom/qcom_scm.c
  31 @@ -806,6 +806,84 @@ bool qcom_scm_pas_supported(u32 peripher
  32  }
  33  EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
  34
  35 +/**
  36 + * qcom_scm_msa_lock() - Lock given peripheral firmware region as MSA
  37 + *
  38 + * @peripheral:        peripheral id
  39 + *
  40 + * Return 0 on success.
  41 + */
  42 +int qcom_scm_msa_lock(u32 peripheral)
  43 +{
  44 +       int ret;
  45 +       struct qcom_scm_desc desc = {
  46 +               .svc = QCOM_SCM_SVC_PIL,
  47 +               .cmd = QCOM_SCM_MSA_LOCK,
  48 +               .arginfo = QCOM_SCM_ARGS(1),
  49 +               .args[0] = peripheral,
  50 +               .owner = ARM_SMCCC_OWNER_SIP,
  51 +       };
  52 +       struct qcom_scm_res res;
  53 +
  54 +       if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
  55 +                                         QCOM_SCM_MSA_LOCK))
  56 +               return 0;
  57 +
  58 +       ret = qcom_scm_clk_enable();
  59 +       if (ret)
  60 +               return ret;
  61 +
  62 +       ret = qcom_scm_bw_enable();
  63 +       if (ret)
  64 +               return ret;
  65 +
  66 +       ret = qcom_scm_call(__scm->dev, &desc, &res);
  67 +       qcom_scm_bw_disable();
  68 +       qcom_scm_clk_disable();
  69 +
  70 +       return ret ? : res.result[0];
  71 +}
  72 +EXPORT_SYMBOL_GPL(qcom_scm_msa_lock);
  73 +
  74 +/**
  75 + * qcom_scm_msa_unlock() - Unlock given peripheral MSA firmware region
  76 + *
  77 + * @peripheral:        peripheral id
  78 + *
  79 + * Return 0 on success.
  80 + */
  81 +int qcom_scm_msa_unlock(u32 peripheral)
  82 +{
  83 +       int ret;
  84 +       struct qcom_scm_desc desc = {
  85 +               .svc = QCOM_SCM_SVC_PIL,
  86 +               .cmd = QCOM_SCM_MSA_UNLOCK,
  87 +               .arginfo = QCOM_SCM_ARGS(1),
  88 +               .args[0] = peripheral,
  89 +               .owner = ARM_SMCCC_OWNER_SIP,
  90 +       };
  91 +       struct qcom_scm_res res;
  92 +
  93 +       if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
  94 +                                         QCOM_SCM_MSA_UNLOCK))
  95 +               return 0;
  96 +
  97 +       ret = qcom_scm_clk_enable();
  98 +       if (ret)
  99 +               return ret;
 100 +
 101 +       ret = qcom_scm_bw_enable();
 102 +       if (ret)
 103 +               return ret;
 104 +
 105 +       ret = qcom_scm_call(__scm->dev, &desc, &res);
 106 +       qcom_scm_bw_disable();
 107 +       qcom_scm_clk_disable();
 108 +
 109 +       return ret ? : res.result[0];
 110 +}
 111 +EXPORT_SYMBOL_GPL(qcom_scm_msa_unlock);
 112 +
 113  static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
 114  {
 115         struct qcom_scm_desc desc = {
 116 --- a/drivers/firmware/qcom/qcom_scm.h
 117 +++ b/drivers/firmware/qcom/qcom_scm.h
 118 @@ -102,6 +102,8 @@ struct qcom_tzmem_pool *qcom_scm_get_tzm
 119  #define QCOM_SCM_PIL_PAS_SHUTDOWN      0x06
 120  #define QCOM_SCM_PIL_PAS_IS_SUPPORTED  0x07
 121  #define QCOM_SCM_PIL_PAS_MSS_RESET     0x0a
 122 +#define QCOM_SCM_MSA_LOCK              0x24
 123 +#define QCOM_SCM_MSA_UNLOCK            0x25
 124
 125  #define QCOM_SCM_SVC_IO                        0x05
 126  #define QCOM_SCM_IO_READ               0x01