git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 8c40d99e5f43e0545a3f4fea9156313847e2eb79 Mon Sep 17 00:00:00 2001
   2 From: Heiner Kallweit <hkallweit1@gmail.com>
   3 Date: Wed, 9 Apr 2025 21:05:37 +0200
   4 Subject: [PATCH] r8169: add helper rtl_csi_mod for accessing extended config
   5  space
   6
   7 Add a helper for the Realtek-specific mechanism for accessing extended
   8 config space if native access isn't possible.
   9 This avoids code duplication.
  10
  11 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
  12 Link: https://patch.msgid.link/b368fd91-57d7-4cb5-9342-98b4d8fe9aea@gmail.com
  13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  14 ---
  15  drivers/net/ethernet/realtek/r8169_main.c | 26 ++++++++++++++---------
  16  1 file changed, 16 insertions(+), 10 deletions(-)
  17
  18 --- a/drivers/net/ethernet/realtek/r8169_main.c
  19 +++ b/drivers/net/ethernet/realtek/r8169_main.c
  20 @@ -2856,10 +2856,23 @@ static u32 rtl_csi_read(struct rtl8169_p
  21                 RTL_R32(tp, CSIDR) : ~0;
  22  }
  23
  24 +static void rtl_csi_mod(struct rtl8169_private *tp, int addr,
  25 +                       u32 mask, u32 set)
  26 +{
  27 +       u32 val;
  28 +
  29 +       WARN(addr % 4, "Invalid CSI address %#x\n", addr);
  30 +
  31 +       netdev_notice_once(tp->dev,
  32 +               "No native access to PCI extended config space, falling back to CSI\n");
  33 +
  34 +       val = rtl_csi_read(tp, addr);
  35 +       rtl_csi_write(tp, addr, (val & ~mask) | set);
  36 +}
  37 +
  38  static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp)
  39  {
  40         struct pci_dev *pdev = tp->pci_dev;
  41 -       u32 csi;
  42         int rc;
  43         u8 val;
  44
  45 @@ -2876,16 +2889,12 @@ static void rtl_disable_zrxdc_timeout(st
  46                 }
  47         }
  48
  49 -       netdev_notice_once(tp->dev,
  50 -               "No native access to PCI extended config space, falling back to CSI\n");
  51 -       csi = rtl_csi_read(tp, RTL_GEN3_RELATED_OFF);
  52 -       rtl_csi_write(tp, RTL_GEN3_RELATED_OFF, csi & ~RTL_GEN3_ZRXDC_NONCOMPL);
  53 +       rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0);
  54  }
  55
  56  static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
  57  {
  58         struct pci_dev *pdev = tp->pci_dev;
  59 -       u32 csi;
  60
  61         /* According to Realtek the value at config space address 0x070f
  62          * controls the L0s/L1 entrance latency. We try standard ECAM access
  63 @@ -2897,10 +2906,7 @@ static void rtl_set_aspm_entry_latency(s
  64             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
  65                 return;
  66
  67 -       netdev_notice_once(tp->dev,
  68 -               "No native access to PCI extended config space, falling back to CSI\n");
  69 -       csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
  70 -       rtl_csi_write(tp, 0x070c, csi | val << 24);
  71 +       rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24);
  72  }
  73
  74  static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)