1 From 54d989d58d2ac87c8504c2306ba8b4957c60e8dc Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 4 Mar 2025 15:21:08 +0100
4 Subject: [PATCH 1/6] net: airoha: Move min/max packet len configuration in
7 In order to align max allowed packet size to the configured mtu, move
8 REG_GDM_LEN_CFG configuration in airoha_dev_open routine.
10 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
11 Reviewed-by: Simon Horman <horms@kernel.org>
12 Link: https://patch.msgid.link/20250304-airoha-eth-rx-sg-v1-1-283ebc61120e@kernel.org
13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
15 drivers/net/ethernet/airoha/airoha_eth.c | 14 +++++++-------
16 1 file changed, 7 insertions(+), 7 deletions(-)
18 --- a/drivers/net/ethernet/airoha/airoha_eth.c
19 +++ b/drivers/net/ethernet/airoha/airoha_eth.c
20 @@ -138,15 +138,10 @@ static void airoha_fe_maccr_init(struct
24 - for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) {
25 + for (p = 1; p <= ARRAY_SIZE(eth->ports); p++)
26 airoha_fe_set(eth, REG_GDM_FWD_CFG(p),
27 GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM |
29 - airoha_fe_rmw(eth, REG_GDM_LEN_CFG(p),
30 - GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
31 - FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
32 - FIELD_PREP(GDM_LONG_LEN_MASK, 4004));
35 airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK,
36 FIELD_PREP(CDM1_VLAN_MASK, 0x8100));
37 @@ -1521,9 +1516,9 @@ static void airoha_update_hw_stats(struc
39 static int airoha_dev_open(struct net_device *dev)
41 + int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN;
42 struct airoha_gdm_port *port = netdev_priv(dev);
43 struct airoha_qdma *qdma = port->qdma;
46 netif_tx_start_all_queues(dev);
47 err = airoha_set_vip_for_gdm_port(port, true);
48 @@ -1537,6 +1532,11 @@ static int airoha_dev_open(struct net_de
49 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id),
52 + airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id),
53 + GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,
54 + FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |
55 + FIELD_PREP(GDM_LONG_LEN_MASK, len));
57 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG,
58 GLOBAL_CFG_TX_DMA_EN_MASK |
59 GLOBAL_CFG_RX_DMA_EN_MASK);